JPH01207834A - Data processor - Google Patents

Abstract

PURPOSE:To easily detect the error of a control signal by setting the output of a ROM to become one when the control signal becomes a pattern impossible to exist actually. CONSTITUTION:The condition of the one of selecting signal lines 1,000-1,002 becomes on, and the conditions of more than the two lines can not become on. Also, in case of a reading indicating signal line 12 and a writing indicating signal line 13, the condition of either one line becomes on, and the both can not become on at the same time. Consequently, when the more than two lines of the signal lines 1,000-1,002 or 12 and 13 become on at the same time, it is judged as the fault of a control circuit 1. To detect the fault, the condition of the signal lines 1,000-1,002 and 12 and 13 is inputted as the address of a reading dedicated memory (ROM) 3. In case of the fault, the condition of an error detecting signal line 13' is to become on, the fault is noticed to the stop of a system or a host device.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an improvement in a data processing device, and particularly to an error detection method thereof.

(Prior art) In recent years, data processing devices have become more and more complex, and along with this, there is a need to improve reliability. Measures to achieve this include adding parity check bits, duplicating arithmetic circuits, and adding error correction circuits. It is being done.

In each case, the above-mentioned systems were aimed at detecting and correcting errors on the data bus. However, failures can occur in all parts of the data processing device, and the data processing device may send out erroneous control signals.

As an error detection method for this, there is a well-known method in which the data processing devices themselves are duplicated and coincidence detection is performed across all output signals from both data processing devices.
The amount of hardware increases significantly, and this method is often impractical. For this reason, it has been common practice not to perform error checking on control signals.

(Problems to be Solved by the Invention) As mentioned above, in conventional data processing devices, as an error detection method, the data processing devices themselves are duplicated, and the method of performing coincidence across all output signals of both data processing devices is difficult. 5, but this method has the disadvantage that it requires a large increase in hardware and is often impractical. For this reason, it has been common practice not to perform an error check on the control @ signal, which has the disadvantage that errors in the output control signal line cannot be detected.

An object of the present invention is to store invalid turns of the control signal in a read-only memory in advance by utilizing the fact that the output side 1tltl signal is not completely random, but has a certain pattern. It is an object of the present invention to provide a data processing device configured to eliminate the above-mentioned drawbacks by detecting errors in the output control signal line using -F'Ll/C and easily detect errors in the output control signal line.

(Means for Solving the Problems) A data processing device according to the present invention includes a control circuit and a read-only memory.

The control circuit is for sending out a plurality of control signals corresponding to a plurality of controlled devices.

The read-only memory is used to input a control signal as an address and read out invalid patterns of control signals stored in advance.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data processing device according to the present invention. In FIG. 1, 1 is a control circuit of a data processing device, 200 to 202 are controlled devices controlled by the control circuit 1, 3 is a read-only memory (hereinafter referred to as ROM), and 1000 to 1002 are Workpiece @ binding bank, A selection signal line for selecting 200 to 202, 11 is a read instruction signal line, 12 is a write instruction signal line, 13 is an error detection signal line, 14 is a data bus, and 15 is an address bus. be.

The control circuit 1 operates actively and can also be viewed as part of the processor. First, in the write operation to the splitting sub-device 200, the control circuit 1 turns on the state on the selection signal line 1D, turns off the state on the selection signal 1001 and 1002, and selects the splitting bag #200. .

Next, the write data is sent to the data bus 14, and an address specifying an internal register (not shown) of the controlled device 20 is sent to the address bus 15, and the state on the read instruction signal line 11 is is turned off, the state on the write instruction signal line 12 is turned on, and after a certain period of time has elapsed, the state on the write instruction signal line 12 is turned off.

As a result, data is written to a predetermined register inside the controlled device 200. Further, the data transmission onto the data bus 14 and the transmission of the address onto the address bus 15 are stopped, and the state on the selection signal line 100 is turned off.This completes the write operation.

Next, to read data from the split bag #200 to the control circuit 1 or the processor, first turn on the 4 selection signal line 100, turn off the selection signal lines 1001 and 1002, and then Select. After that, an address specifying an internal register (not shown) of the controlled device 200 is sent to the address bus 15, and the state on the write instruction signal line 12 is completely OFF and the state on the read instruction signal line 11 is ON. Make it. As a result, the contents of the register specified in step 15 are sent to the data (step 14) from the internal address of the breaking device 200.

The control circuit 1 or the processor takes in the data on the data bus 14, turns off the state on the read instruction signal line 11, turns off the state on the selection signal line 100, and sends the address onto the address bus 15. Stop. This completes the read operation.

Write/read operations are similarly performed on the controlled devices 201 and 202.

In the above operation, any one of the selection signal lines 1000 and 1002 is turned on, and two or more of them are not turned on. If two or more of them are turned on, there is a failure in the control circuit 1. In the case of the read instruction signal line 11 and the write instruction signal line 12, either one is turned on, and both are not turned on at the same time. If they turn on at the same time, the control circuit 1 is at fault.

To detect such faults, select signal line 1000
~1002, read instruction signal line 11, and are input as addresses of 0M3. #In case of failure, the state of the error detection signal line 13 is turned on, and the system is stopped or a failure is notified to the higher-level device.

Next, FIG. 2 shows a write pattern of the ROM 3 for error detection. In FIG. 2, a to e are address inputs of ROM3, and selection signal lines 1000 to 10, respectively.
02 represents the signal states of the read instruction signal line 11 and the write instruction signal line 12, and f represents the output signal of the ROM 3. %IN in Figure 2 represents the on state,
Blank represents an off state. Therefore, f
Input cover turns for which -IP is displayed in the f column are control signal abnormalities, input cover turns for which %IF is displayed in the f column are control 8 signal abnormalities, and input cover turns for which the f column is blank. This is because it represents a normal control #Il signal.

(Effects of the Invention) As explained above, the present invention enables the addition of a small amount of circuitry by setting the ROM output to be turned on when the control @ signal has a pattern that is actually impossible. This has the effect that failures can be easily detected and the reliability of the device can be improved at low cost.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. FIG. 2 is an explanatory diagram showing the input/output cover turn of the ROM. 1...Control circuit 200-202...Controlled device 3-Fist read-only memory 1000-1002.11.12.13...Signal line 14.16...Path a -e ...ROM address input f...ROM output

Claims (1)

[Claims] A control circuit for externally transmitting a plurality of control signals corresponding to a plurality of controlled devices, and a read-only circuit for inputting the control signals as addresses and reading invalid patterns of the control signals stored in advance. 1. A data processing device comprising a memory.