JP2830491B2 - Bus parity error occurrence detection method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a bus parity error occurrence position in an information processing device such as an input / output control device.

[0002]

2. Description of the Related Art In an information processing device such as an input / output control device, a bus connected to a CPU includes a local bus for the CPU directly connected to the CPU, and a local bus connected to an input / output line adapter. Some functions are divided like a common local bus connecting these local buses. Conventionally, when detecting a failure in such a function-divided bus, the CPU is provided with parity bit generation means for generating a parity bit for information output to the bus, and when a parity error is detected for each local bus, Parity error detection means for activating the bus error line is provided, and when the bus error line becomes active, the CPU determines that a bus failure has occurred.

[0003]

However, in the above-mentioned conventional example, there is a problem that it is not possible to specify which local bus has failed, even if it is possible to detect the occurrence of a failure in the bus. .

An object of the present invention is to provide a bus parity error occurrence position detecting method capable of specifying a local bus in which a fault has occurred.

[0005]

According to the present invention, in order to achieve the above object, a CPU having a bus error line and an address modifier line, and a bus connected to the CPU and comprising a plurality of local buses are provided. In a data processing apparatus including a CPU, a parity generation means for generating a parity bit for information output to the bus by the CPU at the time of a write cycle of the CPU; Parity control means for performing a parity check on the basis of the parity bit thus obtained and the information on the corresponding local bus, activating the bus error line by detecting a parity error, and storing that a parity error has occurred. And the CPU is activated by the activation of the bus error line. Reading the contents and outputs an address where the the address modifier lines are assigned to each parity control means each parity control means stores, it is to determine the failure location on the basis of the read contents.

[0006]

In the write cycle of the CPU, a parity bit for information output from the CPU to the bus is generated by the parity generation means, and based on the parity bit generated by the parity generation means in the parity control means provided for each local bus. The parity check of the information on the corresponding local bus is performed. When each parity control means detects a parity error, it activates the bus error line and stores that a parity error has occurred. When the bus error line becomes active, the CPU outputs the address assigned to each parity control means to the address modifier line to read the contents stored in each parity control means, and the read contents indicate that a parity error has occurred. Of the parity control means indicating
The local bus in which a failure has occurred is specified based on information read from each bus control unit, such as determining that a failure has occurred in the local bus corresponding to the parity control unit closest to the PU.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention, in which a CPU 1, a parity generation unit 2, parity control units 3a to 3c, transceivers 4a to 4c, a device 5
a, 5c and an address modifier line (AM line) 6
Bus error line (BERR line) 7, local address buses 8a to 8c, and local data buses 9a to 9c.
And address parity lines 10a to 10c and data parity lines 11a to 11c.

The CPU 1 has an AM line 6 and a BERR line 7, and can execute exception processing when the BERR line 7 becomes active. The parity generation unit 2 generates a parity bit for data and an address output from the CPU 1 to the local address bus 8a and the local data bus 9a, and generates an address parity line 10a,
Output to the data parity line 11a.

The address parity line 10a and the data parity line 11a are connected to an address parity line 10b and a data parity line 11b via a transceiver 4a, and the address parity line 10b and the data parity line 11b are connected to an address parity line via the transceiver 4b. The line 10c is connected to the data parity line 11c.

The local address bus 8a and the local data bus 9a are local buses for the CPU, and the local address bus 8c and the local data bus 9c are local buses for the input / output line adapter unit and the local address bus 8
b, a local data bus 9b is a common local bus connecting them. The local address bus 8a and the local data bus 9a are connected to the local address bus 8b and the local data bus 9b via the transceiver 4a, and the local address bus 8b and the local data bus 9b are connected to the local address bus 8c via the transceiver 4b. It is connected to the local data bus 9c. A device 5a is connected to the local address bus 8a and the local data bus 9a via the parity control unit 3a, and a device 5c is connected to the local address bus 8c and the local data bus 9c via the parity control unit 3c. I have. The device 5a is a device such as a DMA controller that operates as a bus master, and the data 5c is a device that operates as an input / output line adapter unit.

The parity control units 3a to 3c have a function of detecting a parity error of the local address buses 8a to 8c and the local data buses 9a to 9c, a function of activating the BERR line 7 by detecting a parity error,
A function of storing the detection state of the parity error, and the detection state of the parity error stored by adding the own address via the AM line 6 to the local data bus 9a to 9b.
9c.

FIG. 2 is a block diagram showing an example of the configuration of the parity control unit 3a.
Parity error storage register 33 and register control unit 3
And 4.

The parity check unit 31 detects a parity error based on the address on the local address bus 8a and the parity bit on the address parity line 10a. The parity check unit 32 is connected to the local data bus 9a.
A parity error is detected based on the above data and the parity bit on the data parity line 11a. The parity error storage register 33 includes parity check units 31, 32.
And the parity error detection status at
A parity error occurrence signal 35 is output by storing information indicating the occurrence of a parity error. The register control unit 34 outputs the BERR by outputting the parity error occurrence signal 35 from the parity error storage register 33.
When the address assigned to the own parity control unit 3a is added via the AM line 6, the register 7 outputs the register control signal 36 to output the contents of the parity error storage register 33 to the local data bus 9a. Let it. The other parity control units 3b and 3c have the same configuration as the parity control unit 3a.

FIG. 3 is a diagram for explaining the operation of the embodiment.
FIG. 4 is a flowchart showing an example of the exception processing executed by the CPU 1. The operation of the present embodiment will be described below with reference to the drawings.

When the CPU 1 executes a write cycle in order to transfer data to the device 5c and outputs addresses and data to the local address bus 8a and the local data bus 9a, the parity generation unit 2 causes the CPU 1 to execute the write cycle. A parity bit for an address and data to be output to the local data bus 9a is generated and output to an address parity line 10a and a data parity line 11a.

The parity check units 31 and 32 in the parity control unit 3a perform a parity check on the address on the local address bus 8a and the data on the local data bus 9a, respectively. The information indicating the occurrence of the parity error is stored in the. The register control unit 34 notifies the parity error occurrence signal 3 that the information indicating the occurrence of the parity error has been stored in the parity error storage register 33.
When the detection is made by the step 5, the BERR line 7 is activated. The other parity control units 3b and 3c perform the same operation.

Now, for example, as shown in FIG. 3, if a failure occurs in the local address bus 8a and the local data bus 9a, the parity control unit 3a does nothing because no parity error is detected. The parity control units 3b and 3c perform the above-described operations, store information indicating that a parity error has occurred in the internal parity error storage register 33, and activate the BERR line 7.

When the BERR line 7 becomes active, the CPU 1 executes the following exception processing.

First, an address assigned to the parity control section 3a is output to the AM line 6. When an address assigned to the own parity control unit 3a is added via the AM line 6, the register control unit 34 in the parity control unit 3a adds a register control signal 36 to the parity error storage register 33, and The content (information indicating whether or not a parity error has occurred) stored in the memory 33 is output to the local data bus 9a.
The CPU 1 reads the information output to the local data bus 9a, and then performs the same processing as described above on the parity control unit 3b.

When the above-described processing is performed on all the parity control units 3a to 3c, the CPU 1 performs the exception processing shown in FIG. 4 to specify the local address bus and the local data bus where the parity error has occurred.

First, it is determined whether or not information read from the parity control unit 3a corresponding to the local address bus 8a and the local data bus 9a indicates occurrence of a parity error (S1). If it is determined, the local address bus 8a and the local data bus 9a are determined to be at the fault occurrence position (S2). If not, the process of S3 is performed. In S3, it is determined whether or not the information read from the parity control unit 3b corresponding to the local address bus 8b and the local data bus 9b indicates that a parity error has occurred. If it is determined that the information indicates that a parity error has occurred, the local address is determined. Bus 8
b, it is determined that the local data bus 9b is at the fault occurrence position (S4), and if not, the process of S5 is performed.
In S5, it is determined whether or not the information read from the parity control unit 3c corresponding to the local address bus 8c and the local data bus 9c indicates that a parity error has occurred. If it is determined that the information indicates that a parity error has occurred, the local address bus is determined. 8c, the local data bus 9c is determined to be at the fault occurrence position (S6), otherwise, it is determined that there is no parity error (S7).

In this example, since the information read from the parity control section 3b corresponding to the local address bus 8b and the local data bus 9b indicates the occurrence of a parity error, the CPU 1 causes the local address bus 8b and the local data bus 9b to generate a fault. The position is determined.

In the above-described embodiment, after all the information indicating whether or not a parity error has occurred is read from each of the parity control units 3a to 3c, the exception processing shown in FIG. The local bus in which the error occurred is specified. However, the information is sequentially read from the parity control unit 3a close to the CPU 1, and the local bus corresponding to the parity control unit which first reads the information indicating the occurrence of the parity error has failed. The local bus may be specified.

[0024]

As described above, according to the bus parity error occurrence position detecting method of the present invention, when the occurrence of a parity error is detected for each local bus, the fact is stored and the bus error line is activated. Further, when the bus error line becomes active, an address assigned to each parity control means is output to an address modifier line, and the parity error stored in each parity control means is provided. The CPU causes the CPU to execute an exception process of reading the state of occurrence of the error and specifying the location of the failure based on the read information, so that the local bus in which the failure has occurred can be specified.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration example of a parity control unit.

FIG. 3 is a diagram for explaining the operation of the embodiment.

FIG. 4 is a flowchart illustrating an example of an exception process executed by a CPU.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... CPU 2 ... Parity generation part 3a-3c ... Parity control part 4a-4c ... Transceiver 5a, 5c ... Device 6 ... Address modifier (AM) line 7 ... Bus error (BERR) line 8a-8c ... Local address bus 9a-9c local data bus 10a-10c address parity line 11a-11c data parity line

Claims (3)

(57) [Claims] In an information processing apparatus including a CPU having a bus error line and an address modifier line, and a bus connected to the CPU and comprising a plurality of local buses, a write cycle of the CPU is performed. A parity generation unit for generating a parity bit for information output from the CPU to the bus, and a parity bit provided for each of the local buses, based on information on the local bus corresponding to the parity bit generated by the parity generation unit. Parity control means for making the bus error line active by detecting a parity error and detecting that a parity error has occurred, and wherein the CPU activates the bus error line. Thus, each of the parity control means is connected to the address modifier line. A bus parity error occurrence position detecting method, wherein an address assigned to a stage is output to read out the contents stored in each of the parity control means, and a failure occurrence position is determined based on the read out contents. 2. The CPU outputs an address assigned to each of the parity control means to the address modifier line when the bus error line becomes active, and stores the address in the respective parity control means. And reading out the content and determining that a failure has occurred in the local bus corresponding to the parity control means closest to the CPU among the parity control means in which the read content indicates the occurrence of a parity error. 2. The bus parity error occurrence position detection method according to 1. 3. The CPU outputs the address assigned to each of the parity control means to the address modifier line in order from the parity control means close to the CPU when the bus error line becomes active. The method according to claim 1, wherein the content stored in each of the parity control means is read, and it is determined that a failure has occurred in a local bus corresponding to the parity control means which first reads information indicating the occurrence of a parity error. Item 2. A bus parity error occurrence position detection method according to Item 1.