JP2656600B2 - Test method for semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a test method for testing whether a semiconductor memory device operates normally or not, with the object of reducing test time while ensuring sufficient test accuracy. A large number of cells constituting the area are sequentially selected as base cells, and for each base cell, a cell selected by an address in which one digit address pin is inverted among addresses of the same base cell is sequentially selected as a current cell. A method of testing a semiconductor memory device for detecting whether or not there is a change in cell information of another cell when cell information is written to one of a selected base cell and a current cell, wherein After writing the information,
One of a plurality of current cells corresponding to the one base cell is selected, a test is performed to determine whether information of the selected one current cell has not changed, and this test is continuously repeated for the remaining current cells. The steps to be performed;
After writing information to one base cell, inverting information is written to one of a plurality of current cells corresponding to the one base cell, and then whether the information of the one base cell has not changed is determined. Testing and then repeatedly performing this test on the remaining current cells.

The present invention relates to a test method for testing whether a semiconductor memory device operates normally.

An operation test is performed on a semiconductor memory device such as an SRAM prior to its shipment, but the time required for the operation test has increased with the recent increase in the degree of integration and capacity of the semiconductor memory device. Therefore, there is a demand for a test method capable of shortening the time required for the operation test and reliably detecting an operation failure such as erroneous writing.

[Prior Art] Conventionally, a test pattern for testing whether a semiconductor memory device such as a static RAM operates correctly or not has three test patterns.
Multiplication system, squared system such as Galloping, Diagonal system Galloping
There are 3/2 power multiplication system such as, and 1st power multiplication system such as Marching.

Such a test pattern is for detecting an erroneous write based on a malfunction of the decoder. The cubic multiplication system is different from the first base cell 1 as a base point as shown in FIG. All the cells in the storage area excluding the first and second base cells 1 and 2 are sequentially selected as the current cells 3 from the second base cell 2 out of all the cells in the storage area except for the cell 1 and This is to detect erroneous writing in the combination. Then, the above operation is repeated by sequentially setting all cells in the storage area as the first base cell 1.

In the squaring system shown in FIG. 5, all the cells in the storage area are sequentially selected as base cells 4 serving as base points, and the current cell is selected from all the cells in the storage area excluding the base cell 4 with respect to the base cell 4. 3 are sequentially selected, and erroneous writing in the combination of these cells is detected.

In the 3/2 power multiplying system shown in FIG. 6, the square multiplication is performed in such a manner that a cell located in one diagonal direction with respect to the base cell 4 is sequentially selected as a current cell 3 from among cells arranged in a grid. Different from the system. Further, in the 3/2 power multiplication system, in addition to the base cell, an X character system in which the current cell is sequentially selected in the X character direction, a cross system in which the current cell is sequentially selected in the cross direction, or a rice character direction which is a combination of the above. There is a rice character system to choose. In some cases, the operations of the base cell and the current cell are interchanged with the above operations.

The first power multiplication system does not detect erroneous writing based on a combination of a plurality of cells, but detects erroneous writing by sequentially reading information previously written in each cell.

[Problems to be Solved by the Invention] In each of the test patterns as described above, the time required for the operation test using the test pattern of the cube-multiplier system in which the number of combinations of the base cell and the current cell is large is the longest. The time required by the test pattern is the shortest.

However, with the recent increase in the degree of integration of the semiconductor memory device, there is a problem that the time required for the operation test becomes extremely long with a test pattern of 3/2 power system or higher. In the 1st power multiplication system, the test time can be shortened as compared with the test pattern of the 3/2 power multiplication system or higher, but sufficient test accuracy is secured because erroneous writing cannot be checked based on the address combination. There was a problem that it was not possible.

An object of the present invention is to provide a method of testing a semiconductor memory device capable of coping with high integration of a semiconductor device by shortening a test time while securing sufficient test accuracy.

[Means for Solving the Problems] The object of the present invention is to sequentially select a large number of cells constituting a storage area as base cells, and to invert an address pin of one digit of an address of the base cell for each base cell. Semiconductor that sequentially selects a cell selected by the selected address as a current cell, and detects whether or not the cell information of the other cell changes when cell information is written to one of the selected base cell and the current cell A test method for a storage device, comprising: writing information in one base cell, selecting one of a plurality of current cells corresponding to the one base cell, and selecting information of the selected one current cell. Test whether the current cell has not changed, and then repeat the test for the remaining current cells, and write information to one base cell. Thereafter, the inversion information is written into one of the plurality of current cells corresponding to the one base cell, and then it is tested whether or not the information of the one base cell has changed. And a step of repeatedly executing this test.

[Operation] Since the cell of the address of the base cell whose address pin of one digit is inverted is selected as the current cell, the number of current cells is reduced and the test time is shortened. Further, in addition to selecting a cell at an address where the address pin of one digit where writing error is most likely to occur is inverted as a current cell, and writing information to one base cell, Selecting one of a plurality of current cells to be tested, testing whether or not the information of the selected one current cell has changed, and repeatedly performing the test on the remaining current cells. After writing information to the base cell, writing one inverted information of the plurality of current cells corresponding to the one base cell, and then testing whether the information of the one base cell has not changed, Having the step of repeatedly performing this test on the remaining current cells, while reducing the test time as described above, while performing the repeated test in each step. Suppressing the decrease in the rate of detection of defective cells since there is no step back write There is sufficient ensure test accuracy and be.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings. In a test apparatus 5 shown in FIG. 1, a writing device 7 and a reading device 8 are connected to a CPU 6, and the CPU 6 has an SRAM.
And the like, a program memory 9 storing a program for an operation test of a semiconductor memory device, a base address register 10 for storing an address of a base cell, and storing operation data used for setting a current cell for the base cell. An operation data register 11, a comparison data register 12 for storing comparison data for comparing cell information of the base cell and the current cell, and the like are connected. When an SRAM 13 is connected to the test apparatus 5, for example, as a device under test, an operation test of the SRAM 13 is performed based on a preset test pattern. In the following description, the data stored in the comparison data register 12 is "D".

This test apparatus 5 is the same as the 3/2 power multiplication system of the conventional example in that all the cells of the SRAM 13 are used as base cells, but the current cell has one address pin inverted with respect to the address of the base cell. This is different from the above-described conventional example in that only the cell having the address is selected. That is, for example, "00
Between addresses where only one address pin is inverted, such as an address of "0001" for an address of "00" or an address of "0111" for an address of "0101", select both addresses according to the characteristics of the decoder. Since the probability of malfunctioning is higher than between addresses where a plurality of address pins are inverted, sufficient test accuracy can be ensured by detecting the presence or absence of erroneous writing between addresses where one address pin is inverted. is there.

As a method for obtaining two addresses in which only one address pin is inverted, a method for obtaining an exclusive OR of address data of a base cell and specific operation data is employed. That is, FIGS. 2 (a) and 2 (b)
(C) As shown in (d), for example, the address of the base cell is “0110”, and this address data and “0001” to “10”
When the exclusive OR S with the operation data in which the position of “1” is sequentially shifted as in “00” is obtained, the exclusive OR S is “0111”, “0100”, “0010”, “1110”, respectively. Becomes Accordingly, if the cell having the exclusive OR S as the address is set as the current cell, the current cell having an address obtained by inverting only one address pin with respect to the address of the base cell can be obtained.

Next, the contents of the operation test of the test apparatus 5 operating based on the above-described operation principle will be described with reference to FIGS. 3A and 3B. The SRAM 13 is connected to the test apparatus 5 and the operation test is performed. When started, the CPU 7 first stores "0" as an initial value in the base address register 10 (STEP 1), and inputs "0" as "D" to the comparison data register 12 (ST1).
EP2). That is, "0" is stored in the base address register 10.
Is set, the CPU 6 outputs an address signal of, for example, "0000" to the decoder of the SRAM 13, and the decoder selects the cell of the address. The number of this decoder is
Depends on the type of SRAM, cell is selected by one type of decoder, cell type is selected by two types of decoder for selecting word line and bit line, and two types of cell is selected by word line and bit line , And a decoder that selects a block that divides all the cells into a large number, and the like.
A case where a cell is selected by 4-bit address data whose maximum address is "1000" in the type of decoder will be described.

Following the above operation, CPU 7 is the connected DUT
"D", that is, "0" is written to all the cells of the SRAM 13 (STEP
3) The least significant bit in the operation data register 10 is "1"
Is written to “0001” (STEP 4).

Next, the CPU 6 writes "", that is, "1" based on "0000" stored in the base address register 10 using the cell at the address "0000" of the SRAM 13 as a base cell (STEP
Five). Then, the CPU 6 obtains the exclusive OR S of the data “0000” stored in the base address register 10 and the data “0001” stored in the arithmetic data register 11 as “0001” (STEP
6) The cell whose address is “0001” is set as the current cell. Next, the CPU 6 compares the cell information between the base cell and the current cell (STEP 7). Now, since "1" is written only in the base cell and "0" is written in the other cells, when the cell information of the base cell and the current cell match, "" is written to the base cell. When writing to the current cell, erroneous writing to the current cell has occurred.
The operation test is stopped as an abnormal operation of AM13 (STEP8).

On the other hand, when the cell information of the base cell does not match the cell information of the current cell, the CPU 6 shifts the position of “1” of the operation data of the operation data register 11 by one bit to form the operation data of “0010” (STEP 9). ). Then, the operation data "0
A new current cell is obtained based on “010”, and the above operation is repeated.

After such an operation, when the data stored in the arithmetic data register 11 becomes “1000” and matches the maximum address of the SRAM 13 (STEP 10), the CPU 6 stores “D” in the cell of the address “0000” which was the base cell until then. ”, That is,“ 0 ”is written back to the original state (STEP 11), and the base address register
By adding 1 to the stored data of 10, the address "000
The above operation is repeated with the cell “1” as a new base cell (STEP 12).

Such an operation is repeated and an operation test is performed by sequentially using all the cells of the SRAM 13 as base cells. When the last cell becomes a base cell (STEP 13), the CPU 6 sets the cell information of all the cells to "D", that is, "0". After confirming that (STEP1
4, 15), the data stored in the base address register 10 is set to “0000” again (STEP 16), the data stored in the operation data register is set to “0001” (STEP 17), and the address is stored based on the data stored in the base address register 10. "0000"
Is written as a base address, that is, "1" is written (STEP 18). Then, the current cell is obtained in the same manner as described above, and "D", that is, "0" is written in the current cell (STEPs 19 and 20), and then the cell information of the base cell is read. When the cell information of the base cell changes to “0”, the operation is determined to be abnormal, and the test is stopped (STEPs 21 and 2).
2) If the cell information of the base cell is still “1”, it is determined to be normal and the process proceeds to the next step. That is, the presence or absence of erroneous writing to the base cell when the cell information different from the base cell is written to the current cell is detected.

In this way, the operation data is shifted in each base cell (STEP 23), and such an operation is repeated in all cells (STEPs 17 to 27). Then, when the last cell becomes the base cell, the CPU 6 inverts the content of the data “D” stored in the comparison data register 12, ie, “0”, to “1”.
Based on the new "D", the above operation is repeated again to end the operation test of the SRAM 13 (STEPs 28 and 29).

As described above, in the test pattern of the test apparatus 5, the cell of the address where one address pin in which erroneous writing is most likely to occur is selected as the current cell with respect to the base cell, so that the selected current The number of cells can be significantly reduced compared to the conventional squared multiplication system or the 3/2 power multiplied system to shorten the test time, and also to provide sufficient test accuracy.

The test time can be shortened by incorporating the concept of the test pattern into a square power system or a 3/2 power system.

[Effects of the Invention] As described in detail above, the present invention has an excellent effect of providing a method of testing a semiconductor device capable of shortening a test time while securing sufficient test accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram of a test apparatus that operates according to the test method of the present invention, FIGS. 2 (a), (b), (c) and (d) are explanatory diagrams showing an example of an exclusive OR operation, and FIG. FIGS. 4A and 4B are flow charts showing the operation of the test apparatus.
FIG. 6 and FIG. 6 are explanatory diagrams showing a conventional test pattern. In the figure, 5 is a test apparatus, 6 is a CPU, 10 is a base address register, 11 is an operation data register, 12 is a comparison data register, and 13 is an SRAM.

Continuation of the front page (56) References JP-A 1-2232600 (JP, A) JP-A 2-113499 (JP, A) JP-A 56-119998 (JP, A) JP-B 56-48920 (JP , B1) Japanese Patent Publication No. 56-47640 (JP, B1)

Claims (1)

(57) [Claims] A plurality of cells constituting a storage area are sequentially selected as base cells, and for each base cell, a cell selected by an address obtained by inverting only one digit of the address of the same base cell is selected. A method for testing a semiconductor memory device which sequentially selects as a current cell, and detects whether or not the cell information of the other cell changes when cell information is written to one of the selected base cell and current cell. After writing information in one base cell, one of a plurality of current cells corresponding to the one base cell is selected, and it is determined whether information of the selected one current cell has not changed. Testing, and then repeating this test for the remaining current cells; and writing information to one base cell, and then writing the information to the one base cell. Writing the inversion information into one of the corresponding plurality of current cells, then testing whether the information of the one base cell has changed, and repeatedly performing the test on the remaining current cells. A method for testing a semiconductor storage device, comprising: