JPH02113499A - Memory test method - Google Patents

Abstract

PURPOSE:To test the function in a short time by selecting disturb cells for each test cell and selecting the test cell next and repeating this operation and confirming whether the test cell is good or not. CONSTITUTION:First, a memory device MUT is all reset to 0, and one bit is set to '1' and 9 other bits are set to '0' in address bit inverting registers Q0 to Q9. Thereafter, '1' is written in the cell (test cell) selected by the address of terminals A0 to A9 which are not inverted. After it is confirmed that the cell (disturb cell) selected by the address of terminals A0 to A9 whose one bit indicated by registers Q0 to Q9 is inverted is '0', the address of terminals A0 to A9 is set to the non-inverted state to read out the test cell. This read operation is repeated to test whether test cells and disturb cells are surely distinguished or not, and it is confirmed whether test cells are good or not.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a memory testing method that can test the functionality of a memory in a short time.

[Prior Art] Conventionally, there are various methods for testing memory functions, such as gearing patterns and walking patterns.The most severe method is to focus on a single cell and test Jump to the remaining cells and write or read, and the effect of that operation will be reflected in the IW
This is a pattern to test whether or not it acts on the cell of A, and is a conventional gearropping pattern.

To explain the above gearropping pattern in detail, for example, if the total number of cells is N, first reset all cells to 0' (that is, write 8 times), and then write "1" to the test cell that is the viewpoint. .

Next, after confirming (reading) that any other arbitrary cell is “0”, check whether the information “1” written in the test cell is retained even after the read operation of this arbitrary cell. The test cell is read in order to read out the test cell, and even after the read operation of this test cell, the information of any previous cell is “0”.
0 to reconfirm (read again) whether or not it is retained.
The above three read operations are performed except for the test cell <(N-1
) for arbitrary cells, set the test cell to 0
'' (that is, write 0'' to the test cell) (the test cell is written twice).

Two write operations and 3X for one test cell
(N-1>= (2N-3) read operations are added, so the number of operations is 2+ (3N-3) = (3N-1>).Furthermore, the test cell changes N times, so for all cells (
3N-1)xN= (3N' -N) times, and since it is necessary N times to reset all cells for the first time, 3
Since these operations are performed N2 times and further for 1" and "0", a total of 2×3N2=6N2 operations are required.

Therefore, the time required for the functional test is at least 6N'
Requires X (test cycles). Note that the test cycle is the time required for one read and write operation.

[Problem to be solved by the invention] IC memory has 256 bits per chip, 1 Mbit,
Also, the capacity is now increasing to f&4M bits and 16M bits, and if memory tests such as those mentioned above were performed during the manufacturing process, the time required for such tests increases with the increase in capacity, which has become a serious problem. There is. By the way, if we calculate the test time for large-capacity memory assuming the test cycle is 0.5 μs, it will be approximately 57 hours for 256-bit memory and approximately 916 hours for 1M-bit memory -38
days, approximately 14,660 hours km 11 days for 4 Mbit memory, and approximately 23 days for 16 Mbit memory.
4,562 hours and 9,773 days': It will take 27 years. In this way, if the time required for one test is extremely long, not only inspection during mass production but also testing during design and evaluation will not be practical.

"Means for Solving the Problems" The memory testing method of the present invention provides, for each test cell, an address obtained by inverting any one bit of the address for selecting the test cell when testing the function of a matrix-configured memory. Select the disturb cell selected by
Next, select the test cell and perform a read operation to select the disturb cell again for the disturb cells corresponding to the number of address bits to ensure that the test cell and the disturb cells corresponding to the number of address bits are connected. The present invention is characterized in that it tests whether the memory cells can be distinguished and selected, and also checks whether the test cells are good or bad, and tests so that all the memory cells are sequentially selected as test cells for the test.

[Example] Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a concrete block diagram of a memory testing method according to an embodiment of the present invention.

In FIG. 1, MT is a memory tester and can give addresses to terminals AO to A9. QO-,
-Q9 is an address bit inversion instruction register, and the value is set from the terminals SO to S9 of the memory tester MT, or QO→Q1→Q2→...→Q8→Q
The contents can be shifted in the order of 9→QO. The outputs of the address bit inversion instruction registers QO-Q9 are ANDed with the address inversion signal INV, and then EXORed with the address signals from the terminals AO-A9. When the address inversion signal INV is “1”, the address signal bit corresponding to the bit “1” in the address bit inversion instruction registers QO to Q9 is inverted; on the other hand, when the address inversion signal INV is “0” The address signal is not inverted.

MUT is a matrix memory device of IK bits (32x32=1024 bits) which requires five address selection lines in the bit direction and five in the word direction.

First, the read/write line R from the memory tester MT
/W resets all memory devices fMUT to "0". On the other hand, address bit inversion instruction register QO~Q
9, only one bit from terminals SO to S9 of memory tester MT is "1'°" and the remaining 9 bits are "0".
After that, "1" is written into the selected cell (hereinafter referred to as a test cell) without inverting the addresses of terminals AO to A9.

Next, for @children AO to A9, the cell (hereinafter referred to as a disturb cell) selected by the address in which any one bit specified by the address bit inversion instruction registers QO to Q9 is inverted is "0". Confirm that it exists (read)
After that, in order to check whether the information ``1'' written in the test cell is retained even after the read operation of this disturb cell, the addresses of terminals AO to A9 are not inverted and the test cell is , and then check whether the information “0” of the previous disturb cell is retained even after the read operation of this test cell.
Confirm (reread) by inverting one bit of the addresses O to A9.

The above three read operations are performed to determine if only the 1 bit stored in the address bit inversion instruction registers QO to Q9 is 1".
The address inversion bit positions where the remaining bits are "0" are sequentially shifted and repeated, and for terminals AO to A9, all address bits (number of address bits = The disturb cells selected by 10 different addresses are tested to ensure that they can be selected while being reliably distinguished from the test cells.6 Next, the test cells are written back to "0".

The above-described test cell and disturb cell selection normality test is repeated using all memory cells as test cells to confirm the quality of the entire memory device.

In the following, the case where the test cell information is "1" will be explained, but conversely, the case where the information of the test cell is "O" will be tested in the same way.

FIG. 2 is an explanatory diagram of memory cell selection within a matrix memory in one embodiment of the present invention.

In FIG. 2, the matrix memory has 32 word lines (W
It has 32 bit lines (BitLine) selected by the word line and address bits BO to B4, and the memory cells are selected at the intersection of each word line and bit line. =
1024 bits), W4='''O'', B4=
1/4 partial area of the whole selected by “0” (16x
16=256 bits l-).

As shown in FIG. 1, when the address terminals WO to W4, BO to B4 of the matrix memory MUT are connected to the address terminals AO to A9 of the memory tester MT, the second
When memory cell ■ in the figure is used as a test cell, memory cells ■ to
■ is selected as a disturb cell.

All disturb cells for the test cell are selected to be on the same word line or on the same bit line as the test cell, as shown in FIG. Further, the physical distance from the test cell to the disturb cell is selected in a wide variety from the adjacent cell to the relatively far cell on the opposite end of the line. Here, the disturb cells (2) and (2) are far from the test cell (2), so they are selected outside the area shown in FIG.

In principle, selecting one memory cell is selecting one word line and one bit line, so the word line, bit line Testing the certainty of the selection of is equivalent to testing the selectivity of each memory cell.

As shown in FIG. 2, selection of word lines and bit lines consists of a choice between "0" and "1" for each bit of address bits wo to w4.80 to B4.

Therefore, by testing the certainty of whether each address bit's "0°" is "1" for all address bit patterns (as many as the number of memory cells), all word lines and bits - Equivalent to testing the reliability of line selection, ie, testing the selectivity of each memory cell.

In the present invention, all memory cells of a matrix memory are used as test cells, and all of the disturb cells (as many as the number of address bits) selected by an address obtained by inverting one bit of the address bits for selecting the cell are selected. Since all address bits are tested
The selectivity of each address bit between "0" and "1" is tested for the pattern (as per the number of memory cells), and the selectivity of each memory cell can be tested based on the above-mentioned principle.

Next, consider testing and ensuring the effects of noise and interference between information in matrix memory.

As shown in FIG. 2, noise and interference between information within a matrix memory are mainly caused by propagation through address bit decoding circuits between word lines and bit lines, and by word/interference between memory cells. line, bit
Propagation can occur through lines, as well as through cross talk, leakage, etc. between physically adjacent word lines, bit lines, and memory cells. The effects of propagation through the first address bit decoding circuit are tested along with the selectivity of each memory cell as described above. As explained using FIG. 2, the influence of propagation through the word line and bit line between the second memory cells extends from cells adjacent to the test cell to relatively distant cells on the line. By selecting a variety of representative memory cells as disturb cells and testing memory cell selectivity, the test is performed between memory cells roughly located on the line. The effects of propagation due to cross talk, leakage, etc. between third adjacent word lines, bit lines, and memory cells can be avoided by selecting adjacent cells to the test cell as descoop cells as described above. Tested by testing cell selectivity.

In this way, according to the memory testing method of the present invention, unlike the conventional memory testing method, there is no need to jump to all memory cells, so the test can be completed in a very short time. For example, when a matrix memory in which the number of address bits is K and the total number of cells is NW')K is tested using the method of the present invention, each test cell selects one of the disturb cells, so 3 Adding 2 readings and 2 writings to the test cell (3 + 2>
The result is N times, with all memory cells as test cells.
Since it is performed several times (3, +2>N times, and the first N times of all cell reset writes are added to (3, +2>N + N = 3 (
K+1)N times, repeat these operations again with “0, 1”
”, so the total is 2x3 (K+1)N
= 6 (K+1 >N operations are required. Therefore, compared to the 6N2 operations required by the conventional test method, the number of operations is 6 (K+1)N/6N" = (K+1)/N, 11 in case of K=10 (N=2=1024=IK)
/1024, In the case of K=20 (N=2=1048576=IM), the test time is reduced to 21/1048576.

Here, since N=2, as the capacity of the memory to be tested increases, the time reduction effect becomes exponential. By the way, if the test cycle is 0.5 μs and the test time for large capacity memory is calculated, it will be approximately 15 seconds for 256-bit memory - approximately 66 seconds for 1M bit memory: 1 minute, 4M bit memory In the case of memory, it takes about 289 seconds/5 minutes, and in the case of 16 Mbit memory, it takes about 1258 seconds/21 minutes, which is a significant difference compared to conventional testing methods.

The memory device to which the present invention can be applied is not limited to memory with a two-dimensional (planar) matrix configuration such as IC memory, but also all n-dimensional (n = 1, 2, 3, etc.) matrix configuration memories. It can be used in memory.

[Effects of the Invention] As explained above, according to the present invention, it is possible to perform a functional test in an extremely shorter time than in a conventional memory test, and it is also possible to perform a thorough performance test that is comparable to the conventional test method. Therefore, even for large-capacity memory chips, it is possible to save inspection time at the time of production, and the effect is very large.

[Brief explanation of drawings]

FIG. 1 is a concrete block diagram of a memory testing method according to an embodiment of the present invention, and FIG. 2 is an explanatory diagram of memory cell selection in a matrix memory according to an embodiment of the present invention. MT...Memory tester, QO to Q9...Address bit inversion instruction register, AND...Logical product (AND
) gate, EXOR...exclusive OR (EXOR) gate, MUT...memory device.

Claims (1)

[Claims] 1. When testing the functionality of a matrix-configured memory, for each test cell, select a disturb cell selected by an address in which one bit of the address that selects the test cell is inverted, and then select the disturb cell that selects the test cell. The test cell and the disturb cells corresponding to the number of address bits can be reliably distinguished and selected by sequentially performing a read operation for selecting the disturb cell again for the disturb cells corresponding to the number of address bits. 1. A memory testing method characterized in that the test cell is tested, and the quality of the test cell is also confirmed, and the test is carried out so that all the memory cells are sequentially selected as test cells for the test.