JP2885420B2 - Inspection method of error detection function - Google Patents

Description

Description: Object of the Invention (Industrial Application Field) The present invention relates to an error detection function inspection method, and more particularly to an error detection function of each device provided in a computer system and connected to each other by a bus. It relates to an inspection method for inspection.

(Related Art) In recent computer systems, various error detection functions are provided in each device constituting the system in order to improve reliability. For example, an interface connecting each device via a bus is provided with a bus parity detection function, and a memory device or the like is provided with an error correction function.

However, the conventional computer system is not provided with any function for checking the error detection function itself, and cannot check whether or not the error detection function operates normally. For this reason, in the past, the operation of the error detection function could only be checked when an error occurred in the system operation, and unless the error occurred in the system operation, the error detection function was not inspected and the system as it was as a product There was a disadvantage of being shipped.

(Problems to be Solved by the Invention) Conventionally, it was difficult to inspect the error detection function of each device constituting the computer system, and there was a defect that even if the function was defective, the product was shipped.

The present invention has been made in view of such a point, and an object of the present invention is to provide an error detection function inspection method that can easily inspect the error detection function of each device.

[Configuration of the Invention] (Means for Solving the Problems) The present invention is an inspection method for inspecting an error detection function of each device provided in a computer system and connected to each other by a bus, and A test mode designating means for designating a test mode for testing a function; and bus data switching means for switching data output to the bus according to the test mode designated by the test mode designating means. In this case, the error detection function is checked by performing data input / output that causes various error states to occur in the interface between the devices.

(Operation) In the inspection method of the error detection function, data output to the bus is switched according to the test mode specified by the test mode specifying means, thereby generating various error states. Input / output is performed. Therefore, various types of error detection can be executed for each device connected to the bus, and the error detection function can be checked.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration of a bus interface unit for realizing an inspection method according to an embodiment of the present invention. The bus interface unit is provided in each device constituting the computer system, and receives an address enable signal イ ネ ー ブ ル, a data enable signal ▼, and a response enable signal ▼ via a 1-bit control signal line L1. 32-bit address / data bus line for sending and receiving addresses and data to and from the partner device
In this configuration, parity data for addresses and data is transmitted / received to / from a partner device via a 4-bit parity data bus line L3.

In this interface section, the test register 11
Designates a test mode for checking the error detection function in the own apparatus, and for example, 0 as shown in FIG.
7 to 8 bits. That is, the test data is stored in 0 to 3 bits, the parity error test in the address phase is specified by the fourth bit data, the parity error test in the data phase is specified by the fifth bit data, and the sixth bit data is specified. Designates a dialog error test, and further designates a test of a parity error detection function by data of the seventh bit. The test mode designation signal and the test data are sent to the bus controller 12.

The bus controller 12 includes the driver 30a and the receiver 3
Control signals ▲ ▼, ▲ for line L1 via 0b
The transmission and reception of ▼ and ▲ ▼ are performed, and the multiplexer 14 and the EXOR gates 16 and 17 are controlled according to the test mode designation signal supplied from the test register 11, respectively.

The command / address / data register 13 selectively outputs a data write command, a data read command, a write address, a read address, write data, response data, and the like according to a data transfer phase of the own device.

The multiplexer 14 is controlled by the bus controller 12, selects test data supplied via the bus controller 12 instead of the command output from the command / address / data register 13 in the dialog test mode, and supplies the selected test data to the driver 31a.

The parity data generation circuit 15 is connected to the line L2 via the driver 31a in order to set the number of logical 1 bits in all data obtained by adding parity data to transmission data to an odd number.
The parity data is generated for every 8 bits of the data to be transmitted. This parity data is supplied to the EXOR gate 16.

The EXOR gate 16 receives the control signal and the parity data from the bus controller 12 and outputs the logical output of the EXOR gate 16 to the driver.
Output to the parity data line L3 via 32a. In the parity error test mode in the address phase and the data phase, since the control signal from the bus controller 12 is logic 0, the inverted data of the parity data is output from the EXOR gate 16.

The EXOR gate 17 receives the control signal from the bus controller 12 and the parity data supplied from the partner device via the receiver 32b, and supplies its logical output to the parity check circuit 18. Bus controller in parity error test mode of address phase and data phase
Since the control signal from 12 is logic 0, the inverted data of the parity data is output from the EXOR gate 16.

The parity error check circuit 18 adds the inverted parity data from the EXOR gate 17 to the data from the partner device received by the receiver 32b to check the parity error, and the number of logical 1 bits in all the data is This is to detect whether or not it is an odd number, whereby parity data from the partner device is checked in 8-bit units.

The parity error register 19 is for storing the output of the parity error check circuit 18, and checks whether or not the parity error detection has been normally executed by referring to the contents stored in the register 19. Can be.

The bus error register 20 stores error detection data transferred from the partner device via the address / data bus line L2 in the response phase, and refers to the content stored in the register 21 to store the error detection data of the partner device. The error detection function can be checked.

The reception data register 21 stores data transferred from the partner device via the address / data bus line L2.

Next, the data transfer mode of the interface unit will be described with reference to the timing chart of FIG. FIG. 3 (A) shows the timing of a 16-byte data read operation to the main memory (the other device), and FIG. 3 (B) shows the timing of a 16-byte data write operation to the main memory. It is shown.

First, in the address phase, at the time of writing, a write command and an address of the main memory are sent to the address / data bus line L2, and an address enable signal ▼ is sent to the line L1. Similarly, at the time of reading, the read command and the address of the main memory are sent to the address / data bus line L2, and the address enable signal ▼ is sent to the line L1.

In the data phase, when writing 8-byte data, following the address phase, 4 bytes of data to be written to the memory are first sent to the address / data bus line L2, and the data enable signal
Is sent to the line L1. Subsequently, the next 4 bytes of write data are sent to the address / data bus line L2, and the data enable signal
Sent to L1. When reading data of 8 bytes, the main memory receiving the address phase facilitates the read data, and 4 bytes of the read data are first sent from the main memory to the address / data bus line L2, and the data enable signal is output. ▲ ▼ is the line
Sent to L1. Subsequently, the next 4 bytes of read data and a data enable signal ▼ are sent from the main memory. When writing / reading 4-byte data, the data phase is performed only once.

In the response phase, when the main memory finishes the write process and the read process, error information (bus error, memory error, etc.) in the process and a response enable signal ▼ are output.

Next, the checking operation of the error detection function in each of these data transfer modes will be described. First, a parity error test in the address phase will be described.
When this test mode is specified by the test register 11 and bus access is started, a write command or a read command and an address are sent to the line L2, and an address enable signal ▲ is sent to the line L1.
▼ is sent. Further, parity data according to the information to be transmitted to the line L2 is generated by the parity data generation circuit 15, and the data is inverted by the EXOR gate 16 and transmitted to the line L3. In this case, the operation shifts to the data phase at the time of the write command, but since the main memory has received the inverted parity data, an error is detected and no operation is performed. The bus control unit 12 starts the bus timer and waits for a response from the memory. However, since there is no response, a bus timeout error occurs. That is, in this mode, the inspection of the bus timer monitoring function can be executed. Further, the check of the parity check function of the main memory is also executed at the same time.

Next, the operation of the parity error test in the data phase will be described. This test mode is specified,
When a write command is sent to the bus, in the data phase after the address phase, the write data
The data enable signal ▼ is sent to the line L1 while being sent to L2. Further, parity data according to the write data to be transmitted to the line L2 is generated by the parity data generation circuit 15, and the data is inverted by the EXOR gate 16 and transmitted to the line L3. Thereby, the main memory started in the address phase detects the parity error in the data phase,
No write operation is performed. And from that memory,
In the response phase, the error information and the response enable signal ▼ are transmitted. The error information is stored in the bus error register 20, and the bus error register 20
By referring to the contents of the above, the bus parity error detection function in the data phase of the memory can be checked.

Next, a dialog error test will be described. When this test mode is specified, the test data in the test register 11 is multiplexed in the address phase.
Selected by 14. Therefore, for example, when a write command is set as the test data and a read access is performed in this state, the memory performs a write operation by the write command (test data) while the device itself performs the read access. State. As a result, the memory waits for the write data for a certain period of time, but returns no error information (dialog error) in the response phase because the write data is not supplied. The bus controller 12 of the own device detects a dialog error by returning the response phase without data from the memory. That is, in this mode, a dialog-error test can be executed in both the own device and the memory.

Next, the parity error detection test will be described.
When a read command is sent in the address phase in a state where this test mode is specified, read data is returned from the memory to the line L2 in the data phase, and parity data corresponding to the read data is sent from the memory to the line L3. Is done. Since the parity data is supplied to the parity error check circuit 18 after being inverted by the EXOR gate 17, the check circuit
18 detects a parity error. That is, in this test mode, it is possible to check the parity error detection function of the own device.

As described above, if these test functions are included in a self-diagnosis test or a test program of each device, various bus error detection functions can be easily inspected.

[Effects of the Invention] As described above, according to the present invention, since various error states can be generated, it is possible to easily inspect the error detection function of each device constituting the computer system.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an interface unit for realizing a test method according to an embodiment of the present invention, and FIG. 2 is a specific configuration of a test register provided in the interface unit shown in FIG. FIG. 3 shows the first embodiment.
5 is a timing chart illustrating a data transfer mode of the interface unit illustrated in FIG. 11 Test register, 12 Bus controller, 13
... Command / address / data register, 14 ... Mux, 15 ... Parity data generation circuit, 16,17 ... E
XOR gate, 18 ... Parity error check circuit.

Claims (1)

(57) [Claims] A bus controller; a device connected to the bus controller via a bus; a first error detection circuit provided on the bus controller side; and a second error provided on the device side. A detection circuit; test mode designating means for designating a test mode for checking an error detection function of the first and second error detection circuits; and the bus according to the test mode designated by the test mode designating means. Bus data switching means for switching data to be output to the first and second error detectors by performing data input / output to cause various error states in an interface between the devices at the time of bus access. An error detection function inspection method characterized by inspecting a circuit.