JPS6288047A - Interface controller - Google Patents

Abstract

PURPOSE:To confirm an error detection function at any time in operation in a long hour continuous operation system by constituting a device so that the normal function of the error detection function can be confirmed by the intentional insertion of an error. CONSTITUTION:When an error insertion command is issued from a diagnosis controller, a diagnosis bus control circuit 11 decodes the error insertion command inputted through a diagnosis exclusive bus 28, and sets it at an error insertion instruction circuit 7. An error insertion execution circuit 6 inserts intentionally the error at an output data register 3 or an input data register 4 in the start time of a data transfer. A discrimination circuit 14, when the error cannot be detected notwithstanding the intentional insertion of the error, is operated to terminate the data transfer to an external device 26. Thereby, a data error can be prevented from occurring.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system that is interposed between a central processing unit and a main storage device of a data processing system, and an external device, and that processes the main storage device and the main storage device based on instructions from the central processing unit. The present invention relates to an interface control device that controls data transfer between external devices, and particularly relates to an improvement that makes it possible to confirm the normality of an error detection function during system operation.

[Conventional technology]

Conventionally, this type of interface control device 23 has a central processing unit 21 and a main storage device 22, as shown in FIG.
It is connected via a common input/output bus 25 and to an external device 26, and controls data transfer between the external device 26 and the main storage device 22 according to instructions from the central processing unit 21. Further, the interface control device 23 is also connected to a diagnostic control device 27 via a diagnostic dedicated lot 28 along with other peripheral control devices 24 .

The conventional interface control device 23 is a data transfer side that controls data transfer between the common bus control circuit 8 connected to the common input/output bus 25 and an external device 26 . I11 circuit 16, an error detection circuit 5 for detecting errors in transferred data, an external interface control circuit 12 connected to an external device 26, a common bus control circuit 8, and an external interface control circuit 12 connected to the central processing unit 21. It is comprised of an instruction decoding and execution control circuit 9, etc., which decodes and executes input instructions.

The error detection circuit 5 may be, for example, hardware that performs a vertical parity check on data lines with redundancy, or may perform a cyclic redundancy check (CRC), a horizontal redundancy check character (LRC), or a horizontal parity check. For example, error checking may be implemented primarily by firmware.

When data is transferred between the external device 26 and the main storage device 22 according to a command from the central processing unit 21, the transferred data is checked by the error detection circuit 5, and when the error detection circuit 5 detects an error in the transferred data, the central processing At the same time, the external interface control circuit 12 sends a signal to the external device 26 to stop the data transfer. Further, the state during this time can also be known by the diagnostic control device 27 via the diagnostic bus 28.

In this way, traditional interface system? In the 3'OW setting, the authenticity of transferred data was guaranteed.

Traditional interface system? The error detection function of the III device is checked by running a test as an off-line check by the central processing unit or diagnostic control unit while the system is stopped, and in order to preserve data during data transfer. We are taking all possible precautions.

[Problem that the invention seeks to solve]

The conventional interface control device described above is not designed to test the operation of the error detection function while the system is running, so if the error detection function suddenly fails while the system is running, the normality of the data may be affected. The disadvantage is that there is no guarantee and processing continues with errors.

Furthermore, for example, in a process control system that collects or controls data intermittently over a long period of time, there is a drawback that it is impossible to confirm whether the error detection function is operating normally.

In view of the above-mentioned points, an object of the present invention is to provide an interface control device that allows testing of an error detection function at any time during system operation.

[Means for solving problems]

The interface control device of the present invention comprises: a data transfer control means connected to a common input/output bus of a central processing unit and controlling data transfer between an external device and a main storage device; an error detection means detecting an error in the transferred data; Controls data transfer of the external device and performs error detection of the error detection means.
an external interface control device that controls data transfer between the main storage device and the external device according to a command from the central processing unit, the interface control device controlling data transfer between the main storage device and the external device according to a command from the central processing unit; an error insertion means that intentionally inserts an error into the transfer data based on an error insertion command input from a diagnostic control device connected to an input/output bus via a diagnostic dedicated bus; and a detection result of the error detection means and the above. status register means for storing the fact that an error has been inserted by the error insertion means as a status word and reporting it to the central processing unit; and when the error detection means detects an error due to the error insertion by the error insertion means, the external interface control means (1) determining means for suppressing the output of the transfer stop signal to the external device and causing the external interface control means to output the transfer stop signal to the external device when the error detection means does not detect an error; .

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The interface control device of this embodiment includes a tri-receiver circuit 1 connected to a common input/output bus 25, an external bag T ! :, driver receiver circuit 2 connected to 26,
Output data register 3 and input data register 4 connected between driver receiver circuits l and 2, error detection circuit 5 connected to output data register 3 and input data register 4, connected to output data register 3 and input data register 4 an error insertion execution circuit 6 that executes error insertion based on the error insertion execution circuit 6; an error insertion instruction circuit 7 connected to the error insertion execution circuit 6; A command decoding execution control circuit 9 connected to the Hasu control circuit 8; a data transfer control circuit 1 connected to the command decoding execution control circuit 9;
0, a diagnostic bus control circuit 11 connected to a diagnostic bus 210, an external interface control circuit 12 connected to an instruction decoding/execution control circuit 9, a status register circuit 1 connected to an error detection circuit 5 and an error insertion instruction circuit 7.
3, an error detection circuit 5 and a one-off circuit 14 connected to the error insertion instruction circuit 7.

Next, the operation of the interface control device of this year's example configured as described above will be explained in detail.

An output data register 3 and an input data register 4 are interposed between the driver receiver circuit 1 connected to the common input/output bus 25 and the driver L/ceiver circuit 2 connected to the external device 26. Data input from the output bus 25 is temporarily stored in the output data register 3 and sent to the external device 26 via the driver receiver circuit 2, and data input from the external device 26 to the tri-receiver circuit 2 is stored in the input data register 4. The signal is temporarily stored in and sent to the common input/output lot 25 via the driver/receiver circuit l.

Note that the data path between the driver receiver circuit 1 and the tri-receiver circuit 2 may include data conversion, data width adjustment, and other data processing means;
In FIG. 1, these descriptions are omitted.

Data transfer is from the central processing bag; η to the common lotus control circuit 8
The data transfer command inputted to the command decoding execution control circuit 9
This is done by decoding the data and instructing the data transfer control circuit 10 and external interface control circuit 12 to create ('J1).

The output data of the output data register 3 and the input data register 4 during data transfer is constantly subjected to an error check 2 by an error detection circuit 5. Error checking is performed by parity checking or CRC checking, as in the case of conventional large-scale interface control devices. When an error is detected in the error detection circuit 5, the status is stored in the status register circuit 13 and notified to the central processing unit via the common control circuit 8. At the same time, the judgment circuit 14 performs external interface control. Transfer stop-transmission to external device 26 via circuit 12
Report an error including: and stop the data transfer. Error reporting to the control line 15 is performed via one of the control lines 15.

The error detection circuit 5 can be checked by issuing a 1->-insertion command from the diagnostic control device 6 at any time during operation of the system. That is, when an error insertion command is issued from the diagnostic control device, the diagnostic north control circuit 11 decodes the error insertion command input through the diagnostic lotus 28 and sets it in the error insertion command circuit 7. When an error insertion command is set in the error insertion command circuit 7, the error insertion actual ij circuit 6 outputs data from the output data register 3 or the input data register 4 when data transfer is started.
Insert the error code into. Insertion of errors may be done by any method depending on the nature of the data to be transferred, such as intentionally generating a parity check or query error at any word, or causing one word of data to drop out. I can do it. If the error detection circuit 5 operates normally, the error detected intentionally will be detected by the error detection circuit 5.
The status is stored in the status register circuit 13. The status register circuit 13 also stores a status word indicating that it is in an error insertion state based on the output of the error insertion instruction circuit 7, and the central processing unit and diagnostic control unit detect errors by reading the contents of the status register circuit 13. You can tell whether the function is normal or not.

Furthermore, when an error is intentionally inserted by the output of the error insertion instruction circuit 7 and the output of the error detection circuit 5, the judgment circuit 14 outputs an error detection report from the external interface control circuit 12 to the control line 15. to prevent data transfer from being interrupted. If an error is not detected even though an error is intentionally inserted, the external ink face control circuit 12 immediately operates to cause the external device 26 to stop data transfer.

Therefore, if the error detection function does not operate normally, data transfer can be stopped immediately to prevent data errors.

It goes without saying that measures must be taken to ensure that the transferred data itself does not change due to error insertion.

〔Effect of the invention〕

As explained above, the present invention is configured so that the normality of the error detection function can be confirmed by intentionally inserting an error using an error insertion command from the diagnostic control device.
Even in systems that operate continuously for long periods of time, it is possible to improve data reliability by checking the error detection function at any time during system operation without having to go offline to test the error detection function. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of a data processing system and a conventional interface control device. In the figure, 1.2...Driver receiver circuit, 3...Output data register, 4...Input data register, 5...Error detection circuit, 6...Error insertion Execution circuit, 7...Error insertion instruction circuit, 8...Common bus control circuit, 9...Instruction decoding execution control circuit, IO...Data transfer control circuit, 11. ...Diagnostic bus control circuit, 12...External interface control circuit, 13...
...Status register circuit, 14...Judgment circuit, I5...Control line, 25...Common input/output bus, 26...External device, 28...・This is a diagnostic bus. Patent applicant: NEC Corporation.

Claims (1)

[Scope of Claims] Data transfer control means that is connected to a common input/output bus of the central processing unit and controls data transfer between an external device and the main storage device; and error detection means that detects errors in the transferred data;
external interface control means for controlling data transfer of the external device and stopping the data transfer operation of the external device upon error detection by the error detection means;
In an interface control device that controls data transfer between the main storage device and the external device according to instructions from the central processing unit, input from a diagnostic control device connected to the common input/output bus via a diagnostic dedicated bus is provided. an error insertion means for intentionally inserting an error into the transferred data based on an error insertion command; a detection result of the error detection means and the fact that the error has been inserted by the error insertion means are stored as a status word; status register means for reporting, and when the error detection means detects an error due to error insertion by the error insertion means, the error detection means suppresses output of a transfer stop signal from the external interface control means to the external device; An interface control device characterized in that it includes a determining means for causing the external interface control means to output the transfer stop signal to the external device when the external interface control means does not detect the transfer stop signal.