JPH02148154A - Trouble detecting circuit - Google Patents

Abstract

PURPOSE:To sufficiently cope with the operation after trouble by placing a trouble detecting circuit in a control bus interface part, storing contents of trouble in the detecting part of a trouble detecting part and sending them to a trouble recognizing part in a central processing unit. CONSTITUTION:Trouble detecting circuits 4, 11, and 16 perform the same operation. For example, a trouble detecting circuit 4 is provided with a comparing part 5 and a detecting part 6, and the input value and the output value of the output buffer of a control bus interface part 3 of a main storage device 2 are connected to the comparing part 5, and the comparison result is connected to a trouble detecting part 9 in a central processing unit 7 by a trouble detection signal line 19, and simultaneously contents of trouble are sent to the detecting part 6. A trouble report instruction signal line 22 outputted from the trouble detecting part 9 in the central processing unit is connected to the detecting part 6 in accordance with the result sent to the trouble detecting part 9, and contents in the detecting part 6 are sent to a trouble recognizing part 8 in the central processing unit 7 by trouble contents report signal line 25. Thus, the operation after trouble is sufficiently coped with.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a failure detection circuit, and particularly to a failure detection circuit on the side of a device that drives a control bus.

[Conventional technology]

Conventionally, a failure detection circuit on the device side that drives this type of control bus compares the value output to the control bus with the output value, reports the comparison result to the central processing unit, and compares it on the drive device side. The only thing that was done was to store the contents of the file, and nothing else was done.

[Problem to be solved by the invention]

The conventional failure detection circuit described above only compares the value output to the control bus with the output value, reports the comparison result to the central processing unit, and stores the details of the failure on the driven device side. As a result, even if the central processing unit knows where the failure has occurred, it cannot recognize the nature of the failure and cannot adequately respond to the actions after the failure, resulting in a slight lack of validity and accuracy in the values. There were drawbacks.

[Means to solve the problem]

The failure detection circuit of the present invention has a control bus interface section on the side of a device that drives a control bus, a comparison section that compares a value output to the control bus with an output value, and a detection section that stores detailed contents of the comparison result. and the failure detection signal line that sends the results to the failure detection unit in the solid equipment, and the failure report command line and failure report command line that are output from the failure detection unit in the central processing unit to the detection unit based on the results of the failure detection signal line. The circuit includes a failure description line sent from the detection unit to the failure recognition unit in the central processing unit, and a failure recognition unit in the central processing unit that recognizes the results sent through the failure description line.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The failure detection circuit shown in FIG.・10, 11, comparison units 5, 12, 17, detection units 6, 13, 18, failure detection unit 9, failure recognition/identification unit 8 in central processing unit 7, and failure detection unit 8 in central processing unit 7. Failure detection section 9
, failure l(a detection signal line 1, 20, 21, failure report command signal line 22, 23, 24, failure content report signal line 2)
5, 26, 27 and control bus drive signal lines 2829, 30
It consists of

Each is connected as follows.

The main storage device 2 is connected to the control bus interface unit 3 via the control bus interface unit 3, and the central processing unit 7 is connected to the control bus interface unit 10 via the control bus interface unit 3.
The input/output device 14 is connected to a control bus via a control bus interface section 15. The control bus drive signal line 28 is connected from the central processing unit 7 to the output buffer of the control bus interface unit 3, and the two control bus drive signal lines are connected from the central processing unit 7 to the output buffer of the control bus interface unit 10. , the control bus drive signal 30 is connected from the central processing unit 7 to the output buffer of the control bus interface section 15.

The failure detection circuit 4 has a comparison section 5 and a detection section 6, connects the input value and output value of the output buffer of the control bus interface section 3 of the main storage device 2 to the comparison section 5, and outputs the comparison result as a failure detection signal. It is connected to the failure detection section 9 in the central processing unit 7 through a line 19, and at the same time sends the details of the failure to the detection section 6.

A failure report command signal line 22 output from the failure detection unit 9 in the central processing unit 7 according to the result sent to the failure detection unit 9 is connected to the detection unit 6, and the contents contained in the detection unit 6 are reported as failure details. The signal is sent to the fault recognition unit 8 in the central processing unit 7 via the signal line 25.

Similarly, the failure detection circuit 11 has a comparison section 12 and a detection section 13, and includes a control bus interface section 1 of the central processing unit 7.
The input value and the output value of the output buffer 0 are connected to the comparison unit 5, and the comparison result is connected to the failure detection unit 9 in the central processing unit 7 via the failure detection signal line 20. At the same time, the content of the failure is transmitted to the detection unit 13. send to

A failure report command signal line 23 output from the failure detection unit 9 in the central processing unit 7 according to the result sent to the failure detection unit 9 is connected to the detection unit 13, and the contents contained in the detection unit 13 are converted into a failure content signal. It is sent to the failure recognition unit 8 in the central processing unit 7 via a line 26.

Similarly, the failure detection circuit 16 has a comparison section 17 and a detection section 18, connects the input value and output value of the output buffer of the control bus interface section 15 of the input/output device 14 to the comparison section 17, and compares the result. It is connected to the failure detection section 9 in the central processing unit 7 through the failure detection signal line 21, and at the same time, the details of the failure are sent to the detection section 8. A failure report command signal line 24 output from the failure detection unit 9 in the central processing unit 7 according to the result sent to the failure detection unit 9 is connected to the detection unit 18, and the contents contained in the detection unit 18 are reported as failure details. The signal is sent to the fault recognition unit 8 in the central processing unit 7 via the signal line 27.

A case in which the central processing unit 7 outputs a value to the control bus 1 and a failure occurs will be described below.

Control bus drive signal line 2 output from central processing unit 7
becomes the valid polarity, and the value is output from the central processing unit 7 to the control bus 1. At that time, the control bus interface section 1
If a failure occurs in the output buffer 0, the comparison unit 12 in the failure detection circuit 11 compares the input value and output value of the output buffer of the control bus interface unit 10, determines that there is a failure, and determines the nature of the failure. The failure detection section 9 in the device 7 is notified of the occurrence of a failure through the failure detection line 20, and at the same time, the details of the failure are stored in the detection section 13.

After determining whether there is a failure in the failure detection unit 9, the polarity of the control bus drive signal lines 28, 29, and 30 is checked, and when it is determined that there is a failure in the value output by the central processing unit 7 to the control bus 1, the failure occurs. A signal to report the details of the failure is issued through the report command signal line 23, and the failure details stored in the detection section 13 are sent to the failure recognition section 8 through the failure details report signal line 26.

As a result, the failure recognition unit 8 in the central processing unit 7 can determine that there is a failure in the value output by the central processing unit 7 to the control bus 1, and at the same time know the details.

Since the above operations can also be performed for the main memory operation 2 and the input/output device 14, it is possible to determine which device outputs a value to the control bus 1 when a failure occurs and what the failure is.
Since the central processing unit 7 can be centrally controlled, more accurate values can be communicated and a reliable response can be taken in the event of a failure.

〔Effect of the invention〕

As explained above, the present invention provides a fault detection circuit in each control bus interface section that drives the main memory, central processing unit, input/output device, and control bus, and detects the details of the fault in the detection section in the fault detection section. By storing the data and sending it to the fault recognition unit in the central processing unit, you can learn what kind of content is there and where the output value is erroneous, and you can fully respond to the operation after a fault and fully recognize the validity of the value. This has the effect of increasing the accuracy of the values.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the failure detection circuit of the present invention. DESCRIPTION OF SYMBOLS 1... Control bus, 2... Main storage device, 3... Control bus interface section, 4... Failure detection circuit, 5...
... Comparison section, 6... Detection section, 7... Central processing unit,
8... Failure recognition section, 9... Failure detection section, 10...
Control bus interface unit, 11... Failure detection circuit, 12... Comparison unit, 13... Detection unit, 14... Input/output device, 15... Control bus interface unit,
16... Failure detection circuit, 17... Comparison section, 18...
・Detection section, 19-21... Failure detection signal line, 22-2
4... Failure report command signal line, 25-27... Failure details report signal line, 28-30... Control bus drive signal line.

Claims (1)

[Claims] A central processing unit having a control bus, a main memory, a fault detection section, and a fault recognition section; a control bus interface section consisting of an input/output device and an input/output buffer; a fault detection circuit consisting of a comparison section and a detection section; and a control bus drive. In the information processing device having a signal line, a failure detection signal line, a failure report command signal line, and a failure details report signal line, the main storage device, the central processing unit, and the input/output device are connected to each other via the control bus interface unit. It is connected to the control bus, and connects the input data and output data of the output buffer of the control bus interface section to the comparison section, and transmits the comparison result to the fault detection signal line in the central processing unit. The failure detection unit is connected to the detection unit via the failure report command signal line, and the detection unit is connected to the central processing unit via the failure content report signal line. A failure detection circuit comprising a circuit connected to the failure recognition section in the control bus interface section of each of the main storage device, the central processing unit, and the input/output device.