JPS6235704B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to duplication of storage devices, and particularly to a storage device that allows any portion to be locally duplicated.

As the technology for using electronic computers becomes more sophisticated, online, real-time performance is required, and there is an increasing demand for highly reliable computer systems that cannot tolerate instantaneous interruptions. One of the main causes of system interruption is main storage failure. The main storage device has a part called an operating system that stores programs for managing the entire system, management data, tables, etc., and a part that stores normal application programs and their data. Even if the latter part fails and becomes unrecoverable, the operating system generally returns to a slightly earlier state and retries the process using a normal part of main memory. It is possible. However, if a failure occurs in the former operating system, the system operation must be interrupted because the failure handling function itself cannot be recovered. In order to avoid system interruptions due to failures in the main memory, the main memory is completely duplicated and two main memory devices are provided. Multiplexed and duplex control schemes for performing read operations have been considered. Although such a control method avoids system interruption, it has the disadvantage that it requires two sets of main storage devices, resulting in an enormous amount of equipment. Originally, information on main memory is
There are many programs and tables that can be recovered from external storage that does not change dynamically, and there is relatively little unrecoverable information that should be duplicated and protected. However, completely duplicating the main storage device as described above unnecessarily increases the size and complexity of the device.

An object of the present invention is to avoid system interruption by minimizing local duplication by using any module among a plurality of modules in the main memory as a backup module for duplication. The object of the present invention is to provide a locally duplexable storage device that can be duplicated.

The storage device of the present invention includes a plurality of storage modules, an address register for specifying the storage module, an address decoder for decoding the contents of the address register, and a plurality of storage modules for detecting a failure in the operation of each of the storage modules. and an AND circuit for blocking read data of the storage module by the output of the failure detection circuit, first and second instructions specifying a storage module to be duplicated. matching means for detecting that the content of the address register matches the content of the first instruction means; a gate group to be applied to a storage module, and when the contents of the address register match the contents of the first instruction means, a logic "1" is also applied to the storage module specified by the second instruction means. It is characterized by being configured as follows.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a logic circuit diagram including a partial block diagram showing one embodiment of the present invention. To simplify the explanation, in this example, the main storage device consists of four storage modules of 64 kilobytes each.
Assume that it has a capacity of 256 KB.
That is, the storage modules 41 to 44 each have a capacity of 64 kilobytes, and are assigned module numbers #1 to #4 in order from the lowest address. The addresses for operating the storage device are upper address register (AU) 10 and lower address register (AL) 12.
given from. Upper address register 10 is 2
It consists of bits and is decoded by address decoder circuit 11 to select storage modules 41-44. That is, the address decoder 11 outputs outputs 101, 102, 103, 10 corresponding to the contents "00", "01", "10", "11" of the address register 10.
4 to logic "1". The decoder outputs 101 to 104 are connected to OR circuits 26 to 2, respectively.
9 and module selection lines 126-129, respectively, to the S terminals of storage modules 41-44. An address bus 125 is connected to the address terminals A of the storage modules 41 to 44, and a 16-bit address within the storage module is input from the lower address register 12 to determine the address within the storage module to be operated. Then, a write or read operation is performed by giving a read or write instruction from the operation instruction 99 via the instruction line 135. In the case of writing, the data sent from the data register 30 to each module via the data bus 130 is written to the corresponding address, and in the case of reading, the contents of the corresponding address are output to the readout outputs 131 to 134 of the corresponding storage module. The module selected by the module selection lines 126 to 129 and undergoing a read or write operation is verified to be normal by the corresponding fault detection circuits 51 to 54 by the lines 141 to 144, and the parity of the input data, input address, and output data is verified. If a timing error or incorrect timing is detected, an error signal is output to outputs 151-154. The error signals are sent to a negation circuit 6, respectively.
AND circuits 71 to 74 via 1 to 64, respectively.
By inputting the data into the memory module, read data from the storage module in which the fault has been detected is prevented from being output. Read data 131-134 from a non-faulty storage module is selected in a read operation by being logically ANDed with the negation of the error signal and module selection lines 126-129 by corresponding AND circuits 71-74. The read data of the stored storage module is output. The outputs of AND circuits 71 to 74 are sent to output line 160 via OR circuit 75. The operation of the storage device described above is basically the same as that of a conventional storage device and is well known.

In this embodiment, the above-mentioned address register 10,
12, a first module selection register 13 and a second module selection register 20 are provided.
A 2-bit value indicating a storage module containing information to be duplicated is set in the first module selection register 13. And the second
The module selection register 20 is set with the number of the storage module used to duplicate the storage module. For example, the contents of the first module selection register 13 are set to "01" and the contents of the second module selection register 20 are set to "11". First module selection register 13
The output of is decoded by the decoder 14 and sent to the output line 10.
The corresponding line from 6 to 109 becomes logic "1". The output lines 106 to 109 are input to AND circuits 15 to 18, respectively, and the output line 1 of the decoder 11 is input to the other input of the AND circuits 15 to 18.
01 to 104 are connected to each other.

In this embodiment, the first module selection register 13 and the decoder 14 constitute a first instruction means for specifying a storage module to be duplicated. If the target storage module is fixed,
It may be a device (for example, a resistor connected to a power supply) that simply provides a fixed high level to the inputs of the corresponding AND circuits 15 to 18. Further, the AND circuits 15 to 18 constitute a coincidence detection means for detecting that the content of the address register matches the content of the first instruction means. Therefore, AND circuits 15 to 18 output logic "1" only when the logics of the output lines of decoders 11 and 14 match and become "1".
Output. In other words, when the module specified by the first module selection register 13 is specified by the address register 10, the output of the corresponding AND circuits 15 to 18 becomes logic "1", and the output from the AND circuit is passed through the OR circuit 19. Give "1" to inputs 22-25. The output line 1 of the decoder 21 is connected to the other input of the AND circuits 22 to 25, respectively.
16 to 119 are connected. The decoder 21 is a decoder that decodes the contents of the second module selection register 20. The output of OR circuit 19 is “1”
, the second module selection register 2
Logic "1" is applied to the storage module designated by "0" by corresponding AND circuits 22-25 via OR circuits 26-29. That is, in this embodiment, the address register 20 and the decoder 21
A second module that specifies the storage module to be duplicated with
constitutes an instruction means. When the storage module is fixed, it may simply be something that provides a high level to the corresponding input terminals of the AND circuits 22 to 25 (for example, a resistor connected to a power source). Also, AND circuits 22 to 25 and OR circuits 26 to 29
and constitute a gate group that applies the output of the second instruction means to the corresponding storage module based on the output of the coincidence detection means. For example, when the first module selection register is set to "01" and the second module selection register is set to "11", if "01" is specified by the address register 10, the decoder 11 output 102 is “1”
becomes the storage module 42 via the OR circuit 27.
At the same time, the S terminal of AND circuit 1 is set to “1”.
6. The input of the AND gate 25 is set to "1" via the OR circuit 19, and the output 124 of the AND circuit 25 becomes "1" due to the AND with the output 119 of the decoder 21, and the output of the AND gate 25 is set to "1" via the OR circuit 29. The S terminal of 44 also becomes "1". As a result, storage modules 42 and 44 are connected to address bus 125.
A read or write operation is performed on the address within the storage module given by . That is, a duplication operation is performed. Read or write operations are performed simultaneously according to instructions from the operating instructions 99. on the other hand,
When the address register 10 specifies "00", all outputs of the gate circuits 15 to 18 are "0", so the output 110 of the OR circuit 19 is "0" and the outputs of the gate circuits 22 to 25 are "0". Since both are "0", the output line 1 of the decoder 11
01 to the storage module 4 via the OR circuit 26.
“1” is given only to “1”. Similarly, when the address register 10 specifies "10", only the storage module 43 becomes "1". However, the address register 10 is processed by software so that "11" is not specified.

When the operation is reading, for example, read data from the storage module 42 is input to the AND circuit 72, and is output when no fault is detected. The read data of the storage module 44 is similarly outputted via the AND circuit 74. The output data of the AND circuit 72 and the output data of the AND circuit 74 are the same data, and both are sent out via the OR circuit 75.
However, when a failure occurs in the storage module 42, the output of the failure detection circuit 52 becomes "1".
Since one input of the AND circuit 72 is set to "0" via the NOT circuit 62, reading data from the storage module 42 is blocked. Then, only the correct read data 164 of the storage module 44 is sent out. If a failure occurs in the storage module 44, correct data can be sent out by the output of the storage module 42 in the same way as described above. In this way, even if a failure occurs in one of the storage modules in the duplex configuration, the storage device can output correct data. In this embodiment, only the minimum necessary storage modules are duplicated, so the scale of the storage device does not become very large.Since the parts necessary to maintain system operation are duplicated, system downtime can be avoided. It is possible to avoid this.

FIG. 2 is a logic circuit diagram showing an example of a fault reporting circuit in the case of a fault occurrence in this embodiment. That is, the output lines 151 of the fault detection circuits 51 to 54 in FIG.
154 to the first AND circuit group 80 to 83, the second AND circuit group 85 to 88, and the third AND circuit group 9.
Enter each number from 0 to 93. The output lines 106 to 109 of the decoder 14 in FIG. 1 are connected to the other inputs of the first AND circuit groups 80 to 83, respectively. Further, the second AND circuit group 85 to 8
The other input of 8 is connected to the decoder 21 of FIG.
Output lines 116 to 119 are connected to the output lines 116 to 119, respectively. In addition, the output lines 106 to 109 and 116 to
119 is a NOR circuit group 35 in order.
~38 both inputs, NOR circuit group 35~
Outputs 166-169 of 38 are connected to the other inputs of the third AND circuit groups 90-93, respectively. All the outputs of the first AND circuit group 80 to 83 are input to an OR circuit 84, and the output 175 of the OR circuit 84 is input to an AND circuit 95 and an exclusive OR circuit 97. Said second AND circuit group 85
All outputs of 88 to 88 are input to an OR circuit 89, and an output 180 of the OR circuit 89 is connected to the other inputs of the AND circuit 95 and the exclusive OR circuit 97. Said third AND circuit group 90 to 93
The outputs of the OR circuit 94 are all input to the OR circuit 94, the output 185 of the OR circuit 94 is input to the OR circuit 96, and the output of the AND circuit 95 is connected to the other input of the OR circuit 96. The output 187 of the OR circuit 96 reports a fatal fault. Further, the output 188 of the exclusive OR circuit 97 reports that one of the duplicated storage modules is at fault. That is, report a preliminary failure.

For example, as in the above example, if the first module selection register 13 in FIG. 1 is set to "01" and the second module selection register 20 is set to "11", the output of the decoder Line 107 and output line 119 of decoder 21 are at logic "1". Therefore, when the fault detection circuit 52 detects a fault in the module 42, the fault output 152 becomes logic "1", both inputs of the AND circuit 81 become "1", and the AND circuit 9 is output via the OR circuit 84.
5 and one input of the exclusive OR circuit 97 becomes logic "1". On the other hand, one input of the AND circuit 88 is set to "1" by the output line 119 of the decoder 21, so when the output 154 of the fault detection circuit 54 is "1", the AND circuit 88 outputs "1". Since the other input of the AND circuit 95 is set to "1" via the OR circuit 89, the output of the AND circuit 95 becomes "1" and the output 187 is set to "1" via the OR circuit 96. and report a fatal failure. That is, when a failure occurs in both storage modules 42 and 44, which are the targets of duplication, a fatal failure is reported via the output line 187. However, the output 1 of the fault detection circuit 54
54 is "0", the AND circuit 88
Since the output of the OR circuit 89 is "0", the output of the OR circuit 89 is also "0". Therefore, the output of the AND circuit 95 is "0", and the output 188 of the exclusive OR circuit 97 becomes logic "1". Fault detection circuit 5
2, the output 152 of the fault detection circuit 5 is "0", and the fault detection circuit 5
Similarly, when the output 154 of 4 is "1", the output 188 of the exclusive OR circuit 97 becomes "1". That is, output 188 indicates that one of the duplicated storage modules has failed.

In addition, the output 166 of the NOR circuits 35 to 38
169, the output corresponding to the module not selected by the first and second module selection registers is logic "1". In the example above, output 1
66 and 168 are "1", outputs 167 and 16
9 is "0". Therefore, when the output of the fault detection circuit 51 or 53, that is, 151 or 153 becomes "1", the output of the AND circuit 90 or 92 becomes "1", and the output line 187 is output via the OR circuits 94 and 96. Outputs logic “1” to That is, a failure in a non-duplicated storage module is reported as a fatal failure. These reports allow the operator to take appropriate actions.

In this embodiment, the storage modules to be operated in a duplex manner are the first and second module selection registers 13,
By setting it to 20, it can be set arbitrarily. In addition, when duplex operation is not required, the first and second module selection registers 13 and 2
Just set the same value to 0. For example, when both are set to "00" and the contents of the address register 10 are set to "00", the output 101 of the decoder 11 becomes logic "1" and is input to the OR circuit 26. On the other hand, both inputs of the AND circuit 15 become "1" and "1" is applied to the AND circuit 22 via the OR circuit 19. The other input of the AND circuit 22 is the output 116 of the decoder 21, and since this logic is "1", the AND circuit 22
The output of 2 also becomes "1". Therefore, the OR circuit 26
Only the output of the memory module 41 becomes “1”.
Only the S terminal becomes logic "1". In other words, it is exactly the same as normal addressing. In the fault reporting circuit shown in FIG.
Since only 6 is logic “1”, the fault detection circuit 5
When a failure is detected by output 151 of 1, the outputs of AND circuits 80 and 85 become "1", and both inputs of AND circuit 95 become "1" via OR circuits 84 and 89. Therefore, a logic "1" is output to output 187 via OR circuit 96, and a fatal fault is reported. In other words, it is understood that the operation is the same as in the case without duplication operation.

In the present invention, there is no problem in changing the capacity, number, etc. of the storage modules in the above embodiments, and even when realizing an interlace function in a storage device, a plurality of sets of the configuration of the present invention are provided in each interlace unit. It can be expanded as follows.

As described above, since the present invention is configured so that the minimum necessary storage modules can be duplicated, the necessary duplication can be achieved without increasing the scale of the device so much. This has the effect of avoiding system failure. In other words, the reliability of the storage device can be improved. Note that if the fault reporting circuit is appropriately configured, it is possible to distinguish between fatal faults and preliminary faults and report them.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram including a partial block diagram showing an embodiment of the present invention, and FIG. 2 is a logic circuit diagram showing an example of a failure reporting circuit of the above embodiment. In the figure, 10, 12...address registers,
11...address decoder, 13...first module selection register, 14...first decoder, 20...second
Module selection register, 21...second decoder,
30...Data register, 41-44...Storage module, 51-54...Failure detection circuit, 15-18,
22-25, 71-74, 95...AND circuit, 1
9,26-29,75,84,89,94,96
...OR circuit, 35-38...NOR circuit group, 6
1-64...Negation circuit, 80-83...First AND circuit group, 85-88...Second AND circuit group, 90-9
3... Third AND circuit group, 97... Exclusive OR circuit, 99... Operation instruction.

Claims (1)

[Scope of Claims] 1. A plurality of storage modules, an address register that specifies the storage module, and an address decoder that decodes the contents of the address register;
A storage device comprising: a plurality of failure detection circuits that detect a failure in the operation of each of the plurality of storage modules; and an AND circuit that blocks read data of the storage module by an output of the failure detection circuit. first and second instruction means for specifying a storage module to be duplicated; a coincidence detection means for detecting that the contents of the address register match the contents of the first instruction means; and an output of the coincidence detection means. a group of gates for supplying the output of the second instruction means to the corresponding storage module, and when the content of the address register matches the content of the first instruction means, the second instruction means
1. A locally duplexable storage device, characterized in that the locally duplexable storage device is configured so that a logic “1” is also given to a storage module specified by the instruction means. 2. In the locally duplexable storage device according to claim 1, a first controller inputs the output of the failure detection circuit and the output of the first instruction means.
a group of AND circuits; a second group of AND circuits inputting the output of the fault detection circuit and the output of the second indicating means; and a negative OR circuit inputting the corresponding outputs of the first and second indicating means; and a third AND circuit group that inputs the output of the NOR circuit group and the output of the failure detection circuit, and provides a preliminary failure when a failure occurs in one of the duplicated storage modules. and when a failure occurs in both of the duplicated storage modules or in a non-duplicated storage module, it is reported as a fatal failure.