JPS63231551A - Trouble recovering processing system - Google Patents

Abstract

PURPOSE:To decrease the number of program steps for trouble recovering processing by executing the trouble recovery of a memory group generated an intermittent trouble with a reading instruction and a same writing instruction at the time of the usual action to the memory group. CONSTITUTION:A trouble exists at the key data of a KS1 to a certain KS access address, the trouble does not exist at the key data of a KS2 to the address and the key data trouble of the KS1 is made an intermittent trouble. In the situation, when the reading of KS1-2 to the address is executed, the address is set to a trouble address register 11. Here, the key data recovering processing of the KS1 to the address is executed by reading normal key data, first, with an ISK instruction to the address shown by the trouble address register 11 and writing the read key data to KS1-2 with an SSK instruction. Thus, the number of microprogram steps for the intermittent trouble recovering processing of a memory is minimized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a failure recovery processing method, and more particularly to a failure recovery processing method suitable for recovering from an intermittent failure of a multi-layered memory. 2. Description of the Related Art Conventional devices correct data read from a memory before use, as described in Japanese Unexamined Patent Publication No. 59-60654. However, no consideration was given to the increase in hardware required for data recovery processing in response to intermittent failures in memory and the increase in the number of steps in the failure recovery processing program.

[Problem that the invention seeks to solve]

The above conventional technology increases the number of bits to correct faulty data when recovering from an intermittent fault in memory, increases logic to correct one faulty data, and increases the number of program steps to perform fault recovery processing. There was a problem of increase.

The purpose of the present invention is to simplify the failure recovery processing circuit;
It is possible to reduce the number of steps in the disaster recovery processing program.

[Means for solving problems]

The above purpose is to divide the memory into two parts, wait for a circuit that selects the normal data among the read data, and a register that stores the faulty address, and when a fault occurs, select the faulty address indicated by the register. This is accomplished by executing a program routine that performs memory read and write instructions using the memory.

[Effect]

The circuit is configured to select the normal data between the 21-coded memory and the read data, so that even if one memory fails, as long as the data in the remaining memory is normal, the circuit will always select the normal data. It is possible to read normal data. Therefore, failure recovery can be achieved by writing this normal data to both memories, but reading and writing normal data can be done in exactly the same process as 1 normal process.

〔Example〕

An embodiment of the present invention will be described below using N+.

Solution 1 Figure 1 is a schematic diagram of the present invention.

The storage control device M
The key data is read from the 21 key storages (KS) 1 to 2 in 9, and after the normal data is selected by the selection circuit 7, it is sent to the processing device 8 through the data line 115.
sent to.

When this command, which is a write command (hereinafter abbreviated as SSK command), is sent from the processing device 8 to the storage control device ji9, the key data in the data register 15 in the processing device 8 is sent to the data line 114 according to the instruction 115. The data is written to 2N KS1 to KS2 in the storage control device 9.

When the parity check circuits 4 to 5 detect a fault in the key data read by the ISK command, the signal line 11
6, a failure occurrence report is sent to the processing device 8. The processing device 8 that received this fault occurrence report issues an ISK command and an SS
Start the failure recovery processing program 10 consisting of K instructions,
Recovers from an intermittent failure of key data in KS1 and KS2.

Hereinafter, the ISK command, the SSK command, and the intermittent failure recovery process will be explained in detail with reference to FIG.

FIG. 2 is a detailed diagram of the present invention. In the figure, 1 and 2 are duplicated key storages (KS), and the process of reading key data using an ISK command is performed as follows.

The access address set in the address register 12 through the address line 101 is sent to KS1-2 through the KS address box 102. K for the access address
The data read from S1-2 is passed through the KS read data lines 105-106, and after the normal data is selected by the selection circuit 7, the data is set in the data register 14 through the data line 111. The selection is K
Comparison circuit 3 performs a parity check on the read data of Sl.~2 in parity check circuits 4 and 5, and the result is passed through signal lines 107 to 109 to judgment circuit 6 to determine which data of KSl or 2 is faulty. This is done by determining whether there is a signal and selecting the normal one by passing the signal through 110.

When a failure is detected in at least one of the read data of KS1 and KS2, the access address is saved in the failure address register 11.

The writing of key data to 81 to 2 by the SSK command is performed as follows.The key data that was not supplied from the key data supply fs103 is written to the address set in the address register 12 through the address supply block 101. Set it in the data register 13 and read it to KS1-2 using the KS read data line 104.Currently, there is a failure in the key data of KSl for a certain KS access address, and the key data of KS2 for that address is failure. It is assumed that there is no failure, and the key data failure of KS1 is an intermittent failure. In such a situation, when the offset of KS1 to KS2 is performed for the address, the address is set in the [F address register 11]. Here, the KSl key data recovery process for the address is to first read the normal key data with the ISK command for the address indicated in the 1 failure address register 11, and then transfer the read key data to 88 with the @ command. KS1～
This can be done by writing to 2.

As described above, according to the present invention, there is no need for special hardware for failure recovery, and conventional instructions such as l5KN and SSK can be used.
This enables failure recovery of key data.

〔Effect of the invention〕

According to the present invention, the following effects can be obtained: The number of microprogram steps for the intermittent failure recovery process of the memory is reduced i2, and the special software for the above recovery process is do not need.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a detailed diagram of the storage control device shown in FIG. 1~2...Key storage, 3...Comparison circuit, 4~
5... Parity check circuit, 6... Judgment circuit, 7
. . . selection circuit, 8 . . . processing device, 9 . . . storage control device, 10 . Failure recovery processing program, 11... Failure address register, 12... Address register, 13-15...
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Claims (1)

[Claims] 1. In a memory system comprising a multiplexed memory group, a circuit for selecting normal data from read data from the memory group, and a register group for storing a fault occurrence address of the memory group, the memory A fault recovery processing method characterized in that a memory group in which an intermittent fault has occurred is recovered from a fault by using the same read command and write command for the group during normal operation.