JPS62166401A - Multiplexing system for electronic computer - Google Patents

Abstract

PURPOSE:To surely evade a flaw in control operation due to the abnormality occurrence of a CPU, to perform high-reliability control operation, and to simplify the constitution by using plural CPUs for control operation which store programs having the same contents. CONSTITUTION:The CPUs 2a-2d which control an input/output device 1 store the programs with the same contents and the device 1 outputs a driving signal in response to access signals from the respective CPUs and also outputs a data set ready signal in response to data request signals. Then, if the CPU 2a for control outputs a trouble occurrence signal, the CPU 2b outputs a data request signal to a switching control circuit 5, which closes a gate in response to disable a shift register to operate and also outputs a gate signal to an interface circuit 5b to open gates for an address bus, a data bus, and a control line. Consequently, the CPU 2b transfers specific data to the device 1 and specific control operation is carried on by being backed up by the CPU 2b.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a computer multiplexing system used in a central management device such as a traffic information processing system, a totalizer system, a banking system, or a life support equipment management system. .

(Prior art and its problems) In electronic computers, abnormal failures such as power failures, parity errors in magnetic core storage devices, etc. may occur in the CPUs that make up the computer, and when such failures occur, As a countermeasure, a standby CPU is generally installed in the active CPU, and when an abnormal failure occurs, the standby CPU is
The switch is switched to U so that various control operations can be continued.

However, in recent years, control operations have become more complex, and the frequency of CPU abnormalities has also increased. In a system that is related to life, such as a device management system, the effects of an abnormality in the CPU are significant, and even higher reliability is desired.

Therefore, conventionally, in addition to the active CPU, a plurality of standby CPUs are provided, and these CPUs are monitored by a central processing unit serving as a host computer, so that when an abnormality occurs in the active CPU, the is sensed by the central processing unit, and the data in the active CPU is transferred to the standby CPU.
A multiplex system is configured in such a way that the active CPU is transferred to the standby CPU, and if an error occurs in that standby CPU, the switch is further switched to another standby CPU. was.

However, in the case of the conventional example having such a configuration, a central processing unit is required as a host computer for failure monitoring, which has the drawback of making the configuration complicated and expensive.

(Purpose of the Invention) The present invention has been made in view of the above circumstances, and is an object of the present invention to reliably avoid defective control operations due to CPU abnormalities and to perform highly reliable control operations. The purpose of the present invention is to provide a multiplexing system that is simple in configuration and inexpensive.

(Structure and Effects of the Invention) In order to achieve such an object, the present invention includes three or more CPUs for control operations, each of which stores a program with the same content, and a CPU that responds to an access signal from the CPU. an input/output device that outputs a drive signal and outputs a data set ready signal in response to a data request signal from the CPU; an interface circuit that connects each of the CPUs and the input/output device; a switching control circuit that switches the interface circuit to selectively connect the input/output device in response to a data request signal; and a backup means for outputting a data request signal to the switching control circuit in response to a predetermined fault occurrence signal from another CPU, and the switching control circuit includes the interface circuit. a shift register that sequentially outputs a gate opening signal by step transition; gate means that inputs a data request signal from the CPU to the input/output device in the output state of the gate opening signal; and gate means that inputs a data request signal from the CPU to the input/output device; and step holding means for stopping the step transition of the shift register at the step corresponding to the data request signal until the data set ready signal is stopped after receiving the request signal.

According to this configuration, when an abnormality occurs in a CPU that is performing control operations for an input/output device and a fault occurrence signal is output, another CPU receives the fault occurrence signal and outputs a data request signal. do. When the switching control circuit receives this data request signal, it stops the step shift of the shift register at the step corresponding to the data request signal, holds that step, and outputs the data request signal by the gate opening signal. Connecting the C'PU and the input/output device, inputting the data request signal to the input/output device via the gate means, and receiving the data set ready signal output in response to the data request signal. In the meantime, data is transferred from the CPU to the input/output device, and the normal C
It is backed up by the PU and control operations can be continued.

Therefore, in each of the three or more CPUs for control operation, when an abnormality occurs, a fault occurrence signal is outputted, and when a fault occurrence signal is received, a data request signal is outputted, and the switching control circuit is shifted. It consists of a register, a gate means consisting of a register and a logic gate, and a step holding means consisting of a logic gate, and the process continues until it receives a data set ready signal from an input/output device based on a data request signal from the CPU. During this time, data can be transferred from the CPU to the input/output device for backup, which eliminates the need for a device dedicated to fault monitoring, making the overall system configuration simple and inexpensive.

Moreover, since the same program is stored in each of three or more CPUs for control operation, it is not fixed as an active system or a standby system, and any CPU can be selected in the initial stage. This has the advantage that the control system can be easily designed to perform control operations.

(Description of Examples) Hereinafter, the present invention will be described in detail based on examples shown in the drawings. FIG. 1 is a block diagram according to an embodiment of the present invention. In this figure, ■ indicates input/output devices (CCU, etc.) such as signal control equipment and life support equipment, 2 a, 2 b
, 2c, and 2d are first to fourth CPUs that control the input/output device 1, respectively, and programs having the same content are stored therein.

The input/output device I includes the first to fourth CPUs 2a,
2b, 2c, and 2d, and outputs a drive signal in response to the access signal from the first to fourth
A data set ready signal DTSR is output in response to data request signals DTRQ 1 to 4 from the CPUs 2 a, 2 b, 2 c, and 2 d.

3 is a switching device, and the first to fourth C, P U, 2
Interface circuits 4a, 4b connect address buses, data buses, and control lines between input/output devices I and input/output devices I, respectively.
, 4. c, 4d, and the first to fourth CPUs 2a,
Data request signal DTR from each of 2b, 2c, and 2d
In response to Q 1 to 4, the first to fourth CPUs 2a, 2
Interface circuits 4 a, 4 b, 4 c, 4 d are configured to selectively connect the input/output device I to the input/output device I.
A switching control circuit 5 is provided to switch and control each of them.

As shown in FIG. 2, the switching control circuit 5 includes a circuit 4b that sequentially outputs gate opening signals Gl to 4 by step transition to the interface circuits 4a, 4b, 4-c, and 4d.
The first to fourth . Data request signals 1 to 4 corresponding to data request signals DTRQ 1 to 4 from the CPUs 2a, 2b, 2c, and 2d
gate means 8 for inputting DTRQ to the input/output device 1; CPU 2a, 2b,
Data request signal DTR01~ from 2c, 2d
step holding means 9 for stopping the step transition of the shift register 6 at the step corresponding to the data request signals DTRQ 1 to 4 until the data set ready signal DTSR is stopped after receiving the data set ready signal DTSR. .

The shift register 6 sets Qa=1, Qb, and Qc when the power is turned on and in the initial state of each 4 bits.
, Qd=0.

Below, this Q, a= 1, Qb, Qc, Qd= 0
The case is called the first step TI, and Qb=I,
Qa.

When Qc, Qd=0, the second step T2, Qc=l,
When Qa, Qh, Qd=O, the third step T3, Qd
-1, Qa, Q, b, Qc = 0 in the fourth step T
4 respectively.

In this shift register 6, as mentioned above, when Qa=I, Qb, Qc, and Qd=0, the first step Tl occurs, and when this first step TI, the first C
If there is no first data request signal DTRQI, which is an access signal to the input/output device 1 from the PU, 2a, the data is shifted by one bit by the clock CL1 having a short constant period t, and the process proceeds to the next step T2. First data request signal DTR
Q ], as will be described later, a predetermined operation is performed to output the data set ready signal DTS from the input/output device l.
The step TI is held until receiving R, and after receiving the data set ready signal DTSR, the process proceeds to the next step T2.

The gate means 8 is provided with a first circuit for manually inputting the output from the shift register 6 and data request signals DTRQ 1 to 4 from the first to fourth CPUs 2a, 2b, 2c, and 2d.
Gate circuit 10 and its data request signal DTRQ 1~
A register II and a second gate circuit 12 are provided for outputting data request signals 1 to 4DTRQ corresponding to DTRQ.

The step holding means 9 includes the first to fortieth PU2.
Data request signal DTRQ from a, 2b, 2c, 2d
] to 4, and a third gate circuit I5 that receives the inverted data request signals DTRQ 1 to 4, the data set ready signal DTSR inverted by the inverter 14, and the output from the shift register 6. , a flip-flop I6, and an OR circuit 17. In the figure, 18 is an AND circuit, I9 is a NOR circuit, and 20 is an amplifier circuit.

Each of the first to fourth CPUs 2a, 2b, 2c, and 2d receives a fault occurrence signal HL when an abnormality occurs.
Fault reporting means that outputs T1 to T4 and other CPUs
2 a, 2 b, 2 c, and 2 d. , hereinafter, the failure notification means, the backup means, and the data request signal D
The operation of each of the switching control circuits 5 in response to TRQs 1 to 4 will be explained using the flow chart of FIG. 3 and the time chart of FIG. 4, respectively.

First, 1st to 40th PU 2 a, 2 b,
The operations of the failure notification means and backup means according to 2c and 2d will be explained. Note that in this embodiment, the CPU used for control is the first CPU.
It is called a CPU 2a, and other second to fourth CPUs 2b.

2 c, 2 d, 2nd CPU 2b - 3rd CPU 2C
→The fourth CPU 2d is set to be used for backup in this order.

First, the (n-1)th 1l used for control
- Determine whether a fault occurrence signal HLT (n-1) from the CPU is detected (Fl). However, n=2.3°4.

Here, if the fault occurrence signal HLT(n-1) is sensed,
In response, the data request signal DTRQ (n-1
), the input/output device l is output by the nth CPU.
(F3).

In step F1, the fault occurrence signal HLT(n-
If 1) is not detected, the process moves to step F4, where it is determined whether an abnormality has occurred while the device is being used for control, and if an abnormality has occurred, a fault occurrence signal HLTn is output. If it has not occurred, the process returns to step F1.

A backup means is used to perform the processes from step Fl to step F3 as described above, and step F4 is used as a backup means.
and those that perform the processing in step F5 are respectively referred to as failure notification means.

As shown in FIG. 4, the switching control circuit 5 performs the following operations in response to the data request signal DTRQ1 and the fault occurrence signal HLTI. Note that the normal operation by the first CPU 2a and its first CPU 2a are explained here.
A backup operation by the second CPU 2b in response to an abnormality occurring in the PU 2a will be described as an example.

(1) Normally, the data request signal D is sent from the first CPU 2a to the switching control circuit 5.
When TRQ 1 is output, the data request signal DTR is output when the shift register 6 reaches the first step TI.
In response to Q1, the output from the third gate circuit 15 becomes “L”.
” level, and the shift clock for the shift register 6 is not generated regardless of the first clock CLI, and is held at the first step TI.As a result, the clock continues to flow from the shift register 6 through the amplifier circuit 20. the first gate signal Gl is output to the interface circuit 4a,
The gates of the address bus, data bus, and control lines are opened. At the same time, a data request signal IDTRQ corresponding to the data request signal DTRQ1 is outputted to the input/output device 1 via the first and second gate circuits 10.12 in response to the third clock CL3.

The input/output device 1 receives the data request signal IDTRQ, and in response, outputs the data set ready signal DTS.
R is output to the switching control circuit 5.

] When the data request signal DTRQl from the CPU 2a disappears, in response, the output of the data request signal IDTRQ from the switching control circuit 5 is stopped, and the output of the data set ready signal DTSR is also stopped. When it is confirmed by the second clock CL2 that the data set ready signal DTSR is no longer output, the step holding is canceled by the next clock CLI, and the process moves to the next steps T 2 , T 3 , and T 4 .

As a result, while the first step TI is held, predetermined data is transferred from the first CPU 2a to the input/output device 1, and predetermined control operations are performed by the first CPU 2a.

(11) When an abnormality occurs When an abnormality occurs in the first CPU 2a, the fault notification means outputs a fault occurrence signal HLTI, and when the second CPU 2b receives this fault occurrence signal HLTI, the second CPU 2b responds to the fault occurrence signal HLTI. Data request signal DTRQ2
Output.

A data request signal D is sent from the second CPU 2b to the switching control circuit 5.
When TRQ2 is output, the data request signal DTRQ is output when the shift register 6 reaches the second step T2.
2, the output from the third gate circuit 15 goes to the "L" level, and no shift clock is generated for the shift register 6 regardless of the first clock CLI, and the clock is held at the second step T2. As a result, the second gate signal G2 is continuously output from the shift register 6 to the interface circuit 4b via the amplifier circuit 20, and the gates of the address bus, data bus, and control line are opened. At the same time, a data request signal 2D corresponding to the data request signal DTRQ2 is transmitted through the first and second gate circuits 101I2 in response to the third clock CL3.
TRQ is output to the input/output device 1.

The input/output device 1 outputs a data set ready signal DTSR to the switching control circuit 5 in response to the data request signal 2D=15-TRQ.

When the data request signal DTRQ2 from the second CPU 2b disappears, in response, the output of the data request signal 2DTRQ from the switching control circuit 5 is stopped, and the output of the data set ready signal DTSR is also stopped. When the second clock CL2 confirms that the data set ready signal DTSR is no longer output, the step hold is released by the next clock CLI, and the next step T3. T4. I will move on to TI. This results in
While the second step T2 is held, the second CP
Predetermined data is transferred from U2b to the input/output device l, and regardless of an abnormality occurring in the first CPU2a, the second CPU2b
This allows backup and predetermined control operations to be continued.

Thereafter, backup by each of the third and fourth CPUs 2c and 2d is performed in the same manner.

In the above embodiment, there is one CPU 2a for normal control and three CPUs 2b and 2c for backup.
.

2d, but those CPUs 2a, 2
b, 2c.

Each of the 2d has a program with the same content, and it is possible to freely set which one is used for control. Furthermore, the present invention is applicable not only to the case where four CPUs are provided, but also to the case where three or five or more CPUs are provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the computer multiplexing system of the present invention, FIG. 2 is a block diagram showing the configuration of a switching control circuit, and FIG. 3 is a flowchart explaining the operation of the CPU. FIG. 4 is a time chart illustrating the operation of the switching control circuit. 1...I/O device, 2a, 2b, 2c, 2d=-CP
U. 4a, 4b, 4c, 4d-=interface circuit, 5
...Switching control circuit, 6...Shift register, 8...
- Gate means, 9... step holding means.

Claims (1)

[Claims] (1) Three or more CPUs for control operations, each of which stores a program with the same content, and outputs a drive signal in response to an access signal from the CPU, and outputs a drive signal in response to a data request signal from the CPU. an input/output device that outputs a data set ready signal in response to a data set, an interface circuit that connects each of the CPUs and the input/output device, and selectively connects the input/output device in response to a data request signal from the CPU. and a switching control circuit that switches the interface circuit so as to control the interface circuit, and each of the CPUs has a fault notification means that outputs a fault occurrence signal when an abnormality occurs in itself, and a fault notification means that outputs a fault occurrence signal in response to a predetermined fault occurrence signal from another CPU. and a backup means for outputting a data request signal to the switching control circuit in response, and the switching control circuit includes: a shift register that sequentially outputs a gate opening signal to the interface circuit by step transition; gate means for inputting a data request signal from the CPU to the input/output device in the output state of the shift register; step holding means for stopping step transition at a step corresponding to a data request signal.