JP2861595B2 - Switching control device for redundant CPU unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for switching and controlling a duplicated CPU unit.

[0002]

2. Description of the Related Art For example, in a device that requires particularly high reliability, such as a trunk transmission device, a unit is duplicated, that is, a unit is duplicated in order to prevent interruption of a service provided by the device even when a failure occurs. It is redundant. One example of such an apparatus is shown in FIG. This device is the first CP
A plurality of controlled units 4 comprising a U unit 2 and a second CPU unit 3 and connected by a system bus 9
Is controlled by one of these CPU units 2 and 3.

[0003] The CPU units 2 and 3 are
1 and 31, status detection circuits 22 and 23 are provided.
These detection circuits 22 and 23 detect the states of the CPU units 2 and 3, respectively, and output status signals 5 and 6 representing the detection results. The CPU units 2 and 3 further include I / O interfaces 23 and 33,
21 and 31 receive a redundancy control signal 7 from a redundancy control unit 1 described later through interfaces 23 and 33, respectively. When the redundancy control signal 7 is at a high level, the CPU 21 puts its own unit into an operating state, while the CPU 31 puts its own unit into a stopped state. vice versa,
When the redundancy control signal 7 is at a low level, the CPU 21 stops its own unit, while the CPU 31 puts its own unit in an operating state.

The redundancy control unit 1 includes a redundancy control circuit 11, a failure detection circuit 12, and an I / O interface 13. The fault detection circuit 12 detects a fault in the redundancy control unit 1 and notifies the control circuit 11 of the detection result. The redundancy control circuit 11 includes a CPU unit 2,
3, the status signals 5 and 6 are received from the status detection circuits 22 and 32. When the status signal 5 indicates that a failure has occurred in the CPU unit 2, a low-level redundancy control signal is output. When 6 indicates the occurrence of a failure in the CPU unit 3, a high-level redundancy control signal is output. As a result, if a failure occurs in the CPU unit 2, the CP
The U unit 3 operates, and when a failure occurs in the CPU unit 3, the CPU unit 2 operates. Therefore, even if a failure occurs in one of the CPU units 2 and 3,
The controlled unit 4 is controlled by the other CPU unit, and the operation of the entire system is guaranteed.

When a failure occurs in the redundancy control unit 1 and the failure detection circuit 12 detects the failure, the redundancy control circuit 11 outputs a high-level redundancy control signal. Therefore, in this case, the CPU unit 2 is always in the operating state. When the redundancy control unit 1 is not inserted in the slot, the interface 23, 3
The input of 3 is at a high level. Therefore, in this case, the CPU unit 2 always operates.

The interface 13 of the redundancy control unit 1 is connected to the CPU units 2 and 3 as necessary.
It is provided to input data from the PUs 21 and 31 to the redundancy control circuit 11 through the data bus 9.

[0007]

As described above, in a conventional system having a redundant configuration, even if a failure occurs in one of the CPU units, the other CPU unit operates to operate.
The operation of the entire system is guaranteed. However, as described above, when a failure occurs in the redundancy control unit 1 or when the redundancy control unit 1 is not inserted, only one of the predetermined CPU units operates. Further, in the case of a multiple failure in which a failure also occurs in the CPU unit, the operation of the entire system stops even though the other CPU unit is normal.

An object of the present invention is to provide a switching control device for a redundant CPU unit which solves such a problem and guarantees the operation of the entire system even in the case of multiple failures.

[0009]

According to the present invention, there is provided a switching control device for a redundant CPU unit for switching between a first CPU unit and a second CPU unit to be in an operation state or a stop state in accordance with a logical level of a redundancy control signal. , Comprising first and second redundancy control units, wherein the first redundancy control unit comprises: a first failure detection means for detecting a failure of its own unit; and a first redundancy control unit comprising: a first redundancy control unit; Receiving a status signal indicating each state, outputting a first control signal for operating the first or second CPU unit from a first terminal,
When the first failure detection means detects a failure, the first failure detection means includes first redundancy control means for setting the first terminal to high impedance, and the second redundancy control unit comprises: Receiving a status signal indicating a state from each of the first and second CPU units, and receiving the status signal from the first or second CPU unit.
A second control signal for operating the CPU unit is output from a second terminal, and when the second failure detection means detects a failure, the second terminal is set to a high impedance. Redundancy control means for connecting the first and second terminals, and using the first and second control signals as the redundancy control signal as the first and second C signals.
A signal line to be supplied to the PU unit is provided.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 shows an example of a switching control device for a redundant CPU unit according to the present invention. This device switches and operates a first CPU unit 2 and a second CPU unit 3 that control a controlled unit 4 via a CPU bus 9, and includes redundant control units 1 and 8.

First, the CPU unit will be described.
In addition to the above, status detection circuits 22 and 23 are provided. These detection circuits 22 and 23 detect the states of the CPU units 2 and 3, respectively, and status signals 5 and 6 representing the detection results.
Is output. The CPU units 2 and 3 further include I / O interfaces 23 and 33, and the CPUs 21 and 31 receive the redundancy control signal 7 from the redundancy control units 1 and 8 described later through the interfaces 23 and 33, respectively. When the redundancy control signal 7 is at a high level, the CPU 21 sets its own unit to an operating state, while
The PU 31 puts its own unit in a stopped state. Conversely, when the redundancy control signal 7 is at a low level, the CPU 21 stops its own unit, while the CPU 31 puts its own unit in an operating state. Pull-up resistors (not shown) are connected to the input terminals of the interfaces 23 and 33, respectively. Therefore, when the redundant control units 1 and 8 are not inserted or when the output is high impedance, the interface is connected. A high-level redundancy control signal is input to 23 and 33.

The redundancy control unit 1 includes a redundancy control circuit 11, a failure detection circuit 12, and an I / O interface 13. The fault detection circuit 12 detects a fault in the redundancy control unit 1 and notifies the control circuit 11 of the detection result. The redundancy control circuit 11 includes a CPU unit 2,
3, the status signals 5 and 6 are received from the status detection circuits 22 and 32, and when the status signal 5 indicates that a failure has occurred in the CPU unit 2, a low-level redundancy control signal 7 is output. Signal 6
Indicates that a failure has occurred in the CPU unit 3, a high-level redundancy control signal 7 is output. When the failure detection circuit 12 detects the occurrence of a failure,
The redundancy control circuit 11 outputs a high-level redundancy control signal 7
Is output.

The interface 13 of the redundancy control unit 1 is connected to the CPU units 2 and 3 as necessary.
It is provided to input data from the PUs 21 and 31 to the redundancy control circuit 11 through the data bus 9.

The redundancy control unit 8 includes a redundancy control circuit 81, a failure detection circuit 82, and an I / O interface 83. The failure detection circuit 82 detects a failure of the redundancy control unit 8 and notifies the control circuit 81 of the detection result. The redundancy control circuit 81 receives the status signals 5 and 6 from the status detection circuits 22 and 32 of the CPU units 2 and 3. When the status signal 5 indicates that a failure has occurred in the CPU unit 2, the redundancy control circuit 81 has a low-level redundancy. And outputs a high-level redundancy control signal 7 when the status signal 6 indicates that a failure has occurred in the CPU unit 3. When the failure detection circuit 82 detects the occurrence of a failure, the redundancy control circuit 81 outputs a high-level redundancy control signal 7.

The interface 83 of the redundancy control unit 8 is connected to the CPU units 2 and 3 as necessary.
It is provided for inputting data from the PUs 21 and 31 to the redundancy control circuit 81 through the data bus 9.

The output stages of the redundancy control circuits 11, 81 are open collectors or open drains. Therefore, when the control circuits 11, 81 output high-level signals, the outputs of the control circuits 11, 81 are High impedance. The outputs of the control circuits 11 and 81 are directly connected to form a wired OR configuration.

Next, the operation will be described. CPU unit 2,
3 and the redundancy control units 1 and 8 are all normal, the redundancy control circuits 11 and 81 of the redundancy control units 1 and 8 both output the high-level redundancy control signal 7, so that the CPU unit 2 operates and controls the controlled unit 4.

When a failure occurs in the CPU unit 2, the status detection circuit 22 outputs a status signal 5 indicating that a failure has occurred, and as a result, the redundancy control circuits 11, 81
Output a redundancy control signal 7 at a low level. Therefore, the CPU 21 of the CPU unit 2 receives the low-level redundancy control signal 7 through the interface 23 and stops the CPU unit 2. On the other hand, CPU
Since the CPU 31 of the unit 3 receives the low-level redundancy control signal 7 through the interface 33,
The U unit 3 is set to the operating state.

On the other hand, when a failure occurs in the CPU unit 3, the status detection circuit 32 outputs a status signal 6 indicating that a failure has occurred, and as a result, the redundancy control circuit 1
1 and 81 both output a high-level redundancy control signal 7. Therefore, the CPU 21 of the CPU unit 2 receives the high-level redundancy control signal 7 through the interface 23 and puts the CPU unit 2 into an operating state. on the other hand,
The CPU 31 of the CPU unit 3 includes an interface 33
, The CPU unit 3 is stopped.

Next, when the failure detection circuit 12 of the redundancy control unit 1 detects a failure, the redundancy control circuit 11
Outputs a high-level redundancy control signal 7. That is, the redundancy control circuit 11 sets its output to high impedance. As a result, the redundancy control signal 7 output from the redundancy control circuit 81 of the redundancy control unit 8 is supplied to the CPU units 2 and 3,
The CPUs 21 and 31 determine whether to activate or stop their own unit based on the redundancy control signal 7 from the redundancy control circuit 81 operating normally.

On the other hand, when the failure detection circuit 82 of the redundancy control unit 8 detects the occurrence of a failure, the redundancy control circuit 81 outputs a high-level redundancy control signal 7. That is, the redundancy control circuit 81 sets its output to high impedance. As a result, the redundancy control signal 7 output from the redundancy control circuit 11 of the redundancy control unit 1 is supplied to the CPU units 2 and 3, and the CPUs 21 and 31 of the CPU units 2 and 3 operate normally. Based on the redundancy control signal 7 from the redundancy control circuit 11, it is determined whether the own unit is to be operated or stopped.

If one of the redundancy control units 1 and 8 is not inserted into the slot,
The CPUs 21 and 31 of the units 2 and 3 determine whether to activate or stop the own unit based on the redundancy control signal 7 from the redundancy control circuit of the inserted redundancy control unit.

[0023]

As described above, the present invention relates to an apparatus for controlling the first and second CPU units which are activated or deactivated according to the logical level of the redundancy control signal. The first redundancy control unit includes first failure detection means for detecting a failure of its own unit, and first and second CPs.
A status signal indicating each state is received from the U unit, a first control signal for operating the first or second CPU unit is output from a first terminal, and the first fault detecting means detects a fault. Is detected, the first
And a second redundancy control unit that makes the terminal of the second unit have a high impedance. The second redundancy control unit includes a second failure detection unit that detects a failure of the own unit, and a second and a second redundancy control unit.
Receiving a status signal indicating the respective state from the CPU unit, outputs a second control signal for operating the first or second CPU unit from a second terminal, and the second failure detection means When a failure is detected,
Second redundancy control means for setting the second terminal to high impedance, connecting the first and second terminals, and using the first and second control signals as redundancy control signals for the first and second redundancy control signals. And a signal line to be supplied to the CPU unit.

Therefore, in the redundant CPU unit switching control apparatus of the present invention, when a failure occurs in one of the redundant control units, a redundant control signal is supplied from the other redundant control unit to the CPU unit. Is done. Therefore, even when a failure occurs in the redundant control unit together with the CPU unit, the CPU unit can be switched properly, and the operation of the entire system can be guaranteed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a switching control device for a redundant CPU unit according to the present invention.

FIG. 2 is a block diagram showing an example of a conventional redundant CPU unit switching control device.

[Explanation of symbols]

 1,8 Redundancy control unit 2 First CPU unit 3 Second CPU unit 4 Controlled unit 11,81 Redundancy control circuit 12,82 Failure detection circuit 21,31 CPU 22,32 Status detection circuit 13,23,33,83 I / O interface

Claims (1)

(57) [Claims] 1. A switching control device for a redundant CPU unit for switching and controlling a first and a second CPU unit to be in an operation state or a halt state in accordance with a logical level of a redundancy control signal. A redundancy control unit, wherein the first redundancy control unit comprises: first failure detection means for detecting a failure of its own unit; and a status signal indicating each state from the first and second CPU units. Upon receiving the signal, a first control signal for operating the first or second CPU unit is output from a first terminal. When the first failure detecting means detects a failure, And a first redundancy control means for setting a terminal of the second redundancy control unit to a high impedance, wherein the second redundancy control unit detects a failure of its own unit. Receiving status signals indicating the respective states from the first and second CPU units, and outputting a second control signal for operating the first or second CPU unit from a second terminal. And when the second fault detection means detects a fault, the second fault control means includes a second redundancy control means for setting the second terminal to high impedance, and connecting the first and second terminals; A switching control apparatus for a redundant CPU unit, comprising: a signal line for supplying the first and second control signals as the redundant control signal to the first and second CPU units.