JPH0298747A - Multiple controller - Google Patents
Multiple controllerInfo
- Publication number
- JPH0298747A JPH0298747A JP63250932A JP25093288A JPH0298747A JP H0298747 A JPH0298747 A JP H0298747A JP 63250932 A JP63250932 A JP 63250932A JP 25093288 A JP25093288 A JP 25093288A JP H0298747 A JPH0298747 A JP H0298747A
- Authority
- JP
- Japan
- Prior art keywords
- duplex
- dual
- input
- contact
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000009977 dual effect Effects 0.000 claims abstract description 20
- 230000001360 synchronised effect Effects 0.000 claims description 5
- 230000005856 abnormality Effects 0.000 abstract description 3
- 238000001514 detection method Methods 0.000 abstract description 3
- 230000002159 abnormal effect Effects 0.000 abstract description 2
- 230000015654 memory Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 1
Landscapes
- Hardware Redundancy (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は、デュプレックス方式非同期多重装置とデュア
ル方式同期多重装置とを縦統接続した多重制御装置にか
かり、特にデュプレックス側の故障時の誤動作を防止し
た多重制御装置に関するものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a multiplex control device in which a duplex type asynchronous multiplexer and a dual type synchronous multiplexer are cascade-connected, and particularly relates to a multiplex control device in which a duplex type asynchronous multiplexer and a dual type synchronous multiplexer are cascaded. This invention relates to a multiplex control device that prevents malfunctions in the event of a failure.
（従来の技術）
デュプレックス方式非同期多重装置とデュアル方式同期
多重装置とを組合せた多重制御装置の従来のシステム構
成の一例を第４図に示す。(Prior Art) FIG. 4 shows an example of a conventional system configuration of a multiplex control device that combines a duplex type asynchronous multiplexer and a dual type synchronous multiplexer.
第４図において、デュプレックス多重装置１は常用系の
中央処理装置（ｃｐｕ−ｘ） ａと待機系の中央処理装
置（ＣＰＵ−Ｙ） ４および常用系の入出力装置（Ｉｌ
ｏ−Ｘ）と待機系ノ入出力装置（Ｉｌｏ−Ｙ） トから
構成され、デュアル多重装置２は並列に動作する２系統
の中央処理装置（ＣＰＵ−Ａ、 ＣＰＵ−８） ７ 。In FIG. 4, the duplex multiplexing device 1 includes a regular central processing unit (CPU-X) a, a standby central processing unit (CPU-Y) 4, and a regular input/output device (Il).
The dual multiplexer 2 consists of two systems of central processing units (CPU-A, CPU-8) that operate in parallel.
８、デュプレックス側の入出力装置（Ｉｌｏ−Ａ。8. Duplex side input/output device (Ilo-A.
ｌ１Ｏ−８） ９ 、１０および機器側の入出力装置（
Ｉｌｏ−ｃ） ｉｉから構成されており、デュプレック
ス側の常用系とデュアル側の並列系とで多重制御を行う
。またデュプレックス側の常用系と待機系との切換おけ
手動または自動で行われる。l1O-8) 9, 10 and equipment side input/output device (
Ilo-c) ii, and performs multiplex control with the regular system on the duplex side and the parallel system on the dual side. Also, switching between the regular system and the standby system on the duplex side can be done manually or automatically.
（発明が解決しようとする課題）
しかしながら上記従来のシステム構成では、デュプレッ
クス側の故障で入出力装置にデータ更新が無くなった場
合には、デュアル側では故障の判断ができず、待機系に
切換えられずにそのままで制御が継続され、従って正常
な制御が行われず、誤動作によってシステム暴走あるい
はシステムダウンを招く恐れがある。(Problem to be Solved by the Invention) However, in the conventional system configuration described above, if the input/output device no longer updates data due to a failure on the duplex side, the dual side cannot determine the failure and is switched to the standby system. The control continues as it is, and therefore, normal control is not performed, and there is a risk that the system will run out of control or go down due to malfunction.
本発明は、デュプレックス側の故障を、入出力装置を経
由しないで直接にデュアル側で判別してデュプレックス
側を正常な系へ切換え、これによって正常な制御を継続
できる信頼性の高い多重制御装置を提供することを目的
としている。The present invention provides a highly reliable multiplex control device that can directly detect a failure on the duplex side without going through an input/output device, switch the duplex side to a normal system, and thereby continue normal control. is intended to provide.
（課題を解決するための手段および作用）本発明は、デ
ュプレックス方式非同期多重装置とデュアル方式同期多
重装置とを縦続接続した多重制御装置において、デュプ
レックス側の２つの系のそれぞれに正常で且つ現用中で
あるときオンとなる接点を設けること共に、上記２つの
接点のオンオフ状態に応じてデュアル側に入力されるデ
ュプレックス側の系を切換えるロジック回路を設け、こ
れによってデュプレックス側が異常のままでデュアル側
に入力されることを防止し、システム暴走やシステムダ
ウンを防止するようにしている。(Means and effects for solving the problem) The present invention provides a multiplex control device in which a duplex type asynchronous multiplexer and a dual type synchronous multiplexer are connected in cascade. In addition to providing a contact that turns on when This prevents input from occurring and prevents the system from going out of control or going down.
（実施例） 本発明の一実施例を第１図に示す。(Example) An embodiment of the present invention is shown in FIG.
第１図において１人間系の操作指令はデュプレックス装
Ｗ１の入出力装［（Ｉｌｏ−Ｐ） １４を介して入力さ
れる。In FIG. 1, an operation command for one human system is inputted through the input/output device [(Ilo-P) 14 of the duplex equipment W1.
デュプレックス側の常用系ｃｐｕ −ｘおよびデュアル
側並列系ＣＰＵ−Ａ、 ＣＰＵ−８は上記の操作指令に
基づいて演算を行い、ｌ１０−Ｃを介して駆動回路１５
に制御信号を入力し、機器（弁、ポンプモータなど）１
６の制御を行う１以上は従来の第４図の場合と同じ構成
を用いて行われる。The regular system CPU-x on the duplex side and the parallel system CPU-A and CPU-8 on the dual side perform calculations based on the above operation commands, and send them to the drive circuit 15 via l10-C.
Input control signals to equipment (valve, pump motor, etc.) 1
One or more of the controls in step 6 are performed using the same configuration as in the conventional case shown in FIG.
本発明では、さらに故障検出用接点１２．１３が付加さ
れており、接点１２は常用系が現用中で且つ異常が無い
ときオンし、常用系が現用中でないか或いは故障中でオ
フする接点であり、接点１３は待機系が現用中で且つ異
常が無ときオンし、待機系が現用中でないか或いは故障
中でオフする接点である。In the present invention, fault detection contacts 12 and 13 are further added, and the contact 12 is a contact that is turned on when the normal system is in use and there is no abnormality, and is turned off when the normal system is not in use or when there is a failure. The contact 13 is a contact that is turned on when the standby system is in active use and there is no abnormality, and is turned off when the standby system is not in active use or is out of order.
従って、デュプレックス側が正常な常用系または待機系
で運転中であれば、接点１２または接点１３がオンして
デュプレックス側を含む全体のシステムが正常に運転さ
れる。Therefore, if the duplex side is operating as a normal regular system or standby system, contact 12 or contact 13 is turned on and the entire system including the duplex side is operated normally.
すなわち、デュアル側のＣＰＵ−Ａ、 ＣＰＵ−Ｂの入
出カメモリ１７．１８は第２図に示すように、それぞれ
デュプレックス側の常用系ＣＰＵ−Ｘ、 ｌ１０−Ｘか
らの入出力データ１９と待機系ＣＰＵ−Ｙ、 ｌ１０−
Ｙからの入出力データ２０とを含んでおり、常用系が正
常で現用中には接点１２がオンし、且つ待機系が待機中
か故障中で接点１３がオフしていると、第３図に示すよ
うにアンドロジック２１を介して入出力データ１９が使
用され、正常なシステム動作が行われる。That is, as shown in Figure 2, the input/output memories 17 and 18 of the CPU-A and CPU-B on the dual side store the input/output data 19 from the regular CPU-X and l10-X on the duplex side, respectively, and the standby CPU. -Y, l10-
If the normal system is normal and is in use, contact 12 is on, and the standby system is on standby or is out of order and contact 13 is off, as shown in Figure 3. As shown in FIG. 2, the input/output data 19 is used through the AND logic 21, and normal system operation is performed.
同時に正常に待機系に切換えられたときは、接点１２オ
フ、接点１３オンとなり、アンドロジック２２を介して
入出力データ２０が使用され、待機系を介して正常なシ
ステム動作が行われる。At the same time, when the system is normally switched to the standby system, the contact 12 is turned off and the contact 13 is turned on, the input/output data 20 is used via the AND logic 22, and normal system operation is performed via the standby system.
また、接点１２．１３が共にオンまたはオフ（デュプレ
ックス側の両系が共に現用、または共に故障あるいは待
機）になったときはアンドロジック２３または２４を介
してデュプレックス側故障を警報する。Further, when both the contacts 12 and 13 are turned on or off (both systems on the duplex side are in active use, or both are out of order or on standby), a duplex side failure is alerted via the AND logic 23 or 24.
なお上記のロジック演算はそれぞれデュアル側のＣＰＵ
−ＡおよびＣＰＵ −Ｂの内部で行われる。The above logic operations are performed by the CPU on the dual side.
-A and CPU -B.
以上説明したように本発明によれば、デュプレックス多
重装置とデュアル多重装置とを組合せた多重制御装置に
おいて、デュプレックス側の故障状態を確実に検出し、
これによって非正常な状態で制御が継続されることを防
止し、システムダウンやシステム暴走を防止できる信頼
性の高い多重制御装置が実現できる。As explained above, according to the present invention, in a multiplex control device that combines a duplex multiplex device and a dual multiplex device, a failure state on the duplex side can be reliably detected;
As a result, it is possible to realize a highly reliable multiplex control device that can prevent control from being continued in an abnormal state and prevent system failure and system runaway.
第１図は本発明の一実施例を示すシステム構成図、第２
図は本発明におけるデュアル側の入出カメモリエリアの
一例を示す図、第３図は本発明における入出カメモリエ
リア切換用の論理回路図。
第４図は従来の多重制御装置の一例を示すシステム構成
図である。
１・・・デュプレックス多重装置
２・・デュアル多重装置
３・・・デュプレックス常用系中央処理装置Ｉ （ＣＰ
Ｕ−Ｘ）４・・デュプレックス待機系中央処理装置（Ｃ
ＰＵ−Ｙ）５．６，７，８，１１．１４・・・入出力装
置９．１０・・・デュアル中央処理装置（ＣＰＵ−Ａ、
ＣＰＵ−８）１．２．１３・・・故障検出接点
１５・・駆動回路
１６・・・機器
１７、１８・・・入出カメモリ
１９．２０・・・入出力データ
２１〜２４・・・アンドロジック
（８７３３） 代理人 弁理士 猪 股 祥 晃（ほ
か１名）メモｉ二ノｊア
メモリエリア
竿
図
一−
−Ｊ
揄。
翠
図Fig. 1 is a system configuration diagram showing one embodiment of the present invention;
The figure shows an example of the input/output memory area on the dual side in the present invention, and FIG. 3 is a logic circuit diagram for switching the input/output memory area in the present invention. FIG. 4 is a system configuration diagram showing an example of a conventional multiplex control device. 1... Duplex multiplexing device 2... Dual multiplexing device 3... Duplex regular system central processing unit I (CP
U-X) 4... Duplex standby central processing unit (C
PU-Y) 5.6, 7, 8, 11.14... Input/output device 9.10... Dual central processing unit (CPU-A,
CPU-8) 1.2.13... Failure detection contact 15... Drive circuit 16... Equipment 17, 18... Input/output memory 19.20... Input/output data 21-24... AND logic (8733) Agent Patent Attorney Yoshiaki Inomata (and 1 other person) Memo i Ninoj Amemory Area Rod Figure 1--J Comment. green map
Claims (1)
多重装置とを縦続接続した多重制御装置において、デュ
プレックス側の２つの系のそれぞれに正常で且つ現用中
であるときオンとなる接点を設けると共に、上記２つの
接点のオンオフ状態に応じてデュアル側に入力されるデ
ュプレックス側の系を切換えるロジック回路を設けたこ
とを特徴とする多重制御装置。In a multiplex control device in which a duplex type asynchronous multiplexer and a dual type synchronous multiplexer are connected in cascade, each of the two systems on the duplex side is provided with a contact that is turned on when it is normal and in use, and the above two contacts are provided. 1. A multiplex control device comprising a logic circuit that switches a duplex side system input to the dual side according to the on/off state of the dual side.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63250932A JPH0298747A (en) | 1988-10-06 | 1988-10-06 | Multiple controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63250932A JPH0298747A (en) | 1988-10-06 | 1988-10-06 | Multiple controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0298747A true JPH0298747A (en) | 1990-04-11 |
Family
ID=17215165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63250932A Pending JPH0298747A (en) | 1988-10-06 | 1988-10-06 | Multiple controller |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0298747A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010142165A (en) * | 2008-12-19 | 2010-07-01 | Technological Institute Of Organic Function | Improvement for safe growth of plant in open-field hydroponics device |
| JP2010161965A (en) * | 2009-01-15 | 2010-07-29 | Technological Institute Of Organic Function | Improvement of cultivation box |
-
1988
- 1988-10-06 JP JP63250932A patent/JPH0298747A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010142165A (en) * | 2008-12-19 | 2010-07-01 | Technological Institute Of Organic Function | Improvement for safe growth of plant in open-field hydroponics device |
| JP2010161965A (en) * | 2009-01-15 | 2010-07-29 | Technological Institute Of Organic Function | Improvement of cultivation box |
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