JPS60191339A - Redundant digital controller - Google Patents

Redundant digital controller

Info

Publication number
JPS60191339A
JPS60191339A JP59045715A JP4571584A JPS60191339A JP S60191339 A JPS60191339 A JP S60191339A JP 59045715 A JP59045715 A JP 59045715A JP 4571584 A JP4571584 A JP 4571584A JP S60191339 A JPS60191339 A JP S60191339A
Authority
JP
Japan
Prior art keywords
cpu
output
contact
detected
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59045715A
Other languages
Japanese (ja)
Inventor
Yuji Furukubo
雄二 古久保
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59045715A priority Critical patent/JPS60191339A/en
Publication of JPS60191339A publication Critical patent/JPS60191339A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)

Abstract

PURPOSE:To attain the redundant digital control with high reliability by adding a function which turns off forcibly an output through a contact output device in case a CPU is faulty and using an OR gate to switch the CPU. CONSTITUTION:Both CPU-A and CPU-B systems 5 and 6 are always performing the self-diagnosis processing and then turn on the CPU-A and CPU-B system fault signals if the faults of both systems are detected. These fault signals are supplied to the input terminals of forcible open signals of contact output devices 17 and 18 respectively. Therefore the output signal of the device 17 is forcibly turned off regardless of the digital output value of the system 5 when a fault of the system 5 is detected. In the same way, the output signal of the device 18 is forcibly turned off when a fault of the system 6 is detected. In such a way, a contact output device turns off forcibly an output in case a falt is detected in the system 5 or 6. Then both devices 17 and 18 are switched by an OR gate 20.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、中央演算処理ユニットCPUが多重化され
ているディジタル式制御装置の接点出力切換回路を経済
化できる冗長化ディジタル式制御装置に関するものであ
る。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a redundant digital control device that can economize the contact output switching circuit of a digital control device in which central processing units CPUs are multiplexed. be.

〔従来技術〕[Prior art]

従来との種の装置として第1図に示すものかあつた。図
において1はプロセス、2は上記プロセス1を制御する
ための冗長化ディジタル式制御装置である。3,4は上
記プロセス1からの接点入力信号をディジタル信号に変
換するA系及びB系の接点入力装置、7,8は中央演算
処理ユニット(以下CPUという)5,6からのディジ
タル信号を接点信号に変換するA系及びB系の接点出力
装置、10は上記接点出力装置7,8からの信号を選択
的に切換えるスイッチである。また5は2重化された片
系のCPU (以下CPU−A系という)であり、上記
接点入力装置3から制御入力信号値を読み取り、演算処
理後接点出力装置7に出力する。
A conventional type of device was the one shown in FIG. In the figure, 1 is a process, and 2 is a redundant digital control device for controlling the process 1 described above. 3 and 4 are A-system and B-system contact input devices that convert contact input signals from the process 1 into digital signals, and 7 and 8 are contact input devices that convert digital signals from central processing units (hereinafter referred to as CPU) 5 and 6. The A-system and B-system contact output devices convert into signals, and 10 is a switch that selectively switches the signals from the contact output devices 7 and 8. Reference numeral 5 denotes a dual CPU (hereinafter referred to as CPU-A system), which reads control input signal values from the contact input device 3 and outputs them to the contact output device 7 after arithmetic processing.

同様に6は2重化された他の片系のCPU (以下口−
B系)であり、接点入力装置4からの制御入力値を読み
とシ、演算処理後接点出力装置8に出力する。CPU−
A系5及びCPU −B系6の故障検出信号はロジック
回路9に入力する。上記ロジック回路9の出力はスイッ
チ10に入力し、そのスイッチ10の位置を選択する信
号に使われる。
Similarly, 6 is another single-system CPU that is duplicated (hereinafter referred to as
B system) reads the control input value from the contact input device 4, performs arithmetic processing, and outputs it to the contact output device 8. CPU-
The failure detection signals of the A system 5 and the CPU-B system 6 are input to the logic circuit 9. The output of the logic circuit 9 is input to a switch 10 and is used as a signal for selecting the position of the switch 10.

次に動作について説明する。Next, the operation will be explained.

CPU −A系5は接点入力装置3を介して入力したプ
ロセス1からの制御入力信号値に基づいて制御演算を行
ない、その演算結果を接点出力装置7を介してスイッチ
10に出力する。同様にCPU−B系6も接点入力装置
4を介して入力したプロセス1からの制御入力信号値に
基づいて制御演算を行ないその演算結果を接点出力装置
8を介して演算結果をスイッチ10に出力する。上記C
PU−A系5゜CPU −B系6は同様の構成を成し、
全く同じ演算を行なっているため、CPUが両系とも正
常である限り、その演算結果は全く等しい。また、CP
U−A系5は常に自己診断を行ない、その診断の結果異
常が検出されればCPU −A糸故障信号をONにする
The CPU-A system 5 performs control calculations based on the control input signal value from the process 1 input via the contact input device 3, and outputs the calculation result to the switch 10 via the contact output device 7. Similarly, the CPU-B system 6 also performs control calculations based on the control input signal value from the process 1 inputted via the contact input device 4, and outputs the calculation results to the switch 10 via the contact output device 8. do. Above C
The PU-A system 5°CPU-B system 6 has a similar configuration,
Since the exact same calculations are performed, as long as both CPU systems are normal, the results of the calculations will be exactly the same. Also, C.P.
The UA system 5 always performs self-diagnosis, and if an abnormality is detected as a result of the diagnosis, it turns on the CPU-A thread failure signal.

同様にCPU −B系6も常に自己診断を行々っておシ
、異常が検出されればCPU −B系故障信号をONに
する。次に、ロジック回路9は上記のCPU故障信号を
入力し、いずれのCPU出力をプロセス1に出力するか
判断し、その結果をスイッチ10に出力する。上記スイ
ッチ10はロジック回路9の出力に従って切換わり、C
PU出力を選択する。
Similarly, the CPU-B system 6 also constantly performs self-diagnosis, and if an abnormality is detected, the CPU-B system failure signal is turned ON. Next, the logic circuit 9 inputs the above CPU failure signal, determines which CPU output is to be output to the process 1, and outputs the result to the switch 10. The switch 10 is switched according to the output of the logic circuit 9, and C
Select PU output.

例えばロジック回路9はCPUが両系とも正常であれば
スイッチ10に対して現状維持を指令する。
For example, if both CPU systems are normal, the logic circuit 9 instructs the switch 10 to maintain the status quo.

またCPU −A糸故障信号がONになればBを、CP
U−B系故障信号がONになればAを選択するようにス
イッチ10に指示し、万−CPUが両系とも故障したと
きはスイッチ10を双方の系から切離しプロセス1を現
状維持させるような操作を行なう。
Also, if the CPU-A yarn failure signal turns ON, the CPU-A
When the U-B system failure signal turns ON, the switch 10 is instructed to select A, and when both CPU systems fail, the switch 10 is disconnected from both systems and process 1 is maintained as it is. Perform the operation.

従って第1図のような装置ではCPU −A系5.CP
U−B系6のいずれかが正常であればプラントの制御を
支障なく行なえるため、装置全体の信頼性を高くするこ
とができる。
Therefore, in a device like the one shown in FIG. 1, the CPU-A system 5. C.P.
If any one of the U-B systems 6 is normal, the plant can be controlled without any trouble, so the reliability of the entire system can be increased.

従来の冗長化ディジタル式制御装置は上記のように構成
されているので、多重化CPUの出力を切換えるハード
ウェア(例えばロジック回路9.スイッチ10)が必要
となり、装置が複雑になるなどの欠点があった。
Since the conventional redundant digital control device is configured as described above, it requires hardware (for example, a logic circuit 9 and a switch 10) to switch the outputs of multiplexed CPUs, which has the disadvantage that the device becomes complicated. there were.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除去するた
めになされたもので、接点出力装置において外部からの
その出力接点を強制的にオープンできる回路を付加する
ことにより、出力切換ハードウェア(例えばロジック回
路9、スイッチ10)が不要な冗長化ディジタル制御装
置を提供することを目的としている。
This invention was made to eliminate the drawbacks of the conventional devices as described above, and by adding a circuit that can forcibly open the output contact from the outside to the contact output device, output switching hardware (e.g. The purpose of this invention is to provide a redundant digital control device that does not require logic circuits 9 and switches 10).

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を図について説明する。まず
構成を説明すると、第2図において1はプロセス、2は
プロセス1を制御するための冗長化ディジタル式制御装
置である。3,4はプロセス1からの接点入力信号をデ
ィジタル信号に変換する接点入力装置、17,18はC
PU 5 、6からのディジタル信号をリレー駆動信号
に変換して出力接点を動作または不動作する接点出力装
置である。
An embodiment of the present invention will be described below with reference to the drawings. First, the configuration will be explained. In FIG. 2, 1 is a process, and 2 is a redundant digital control device for controlling the process 1. 3 and 4 are contact input devices that convert contact input signals from process 1 into digital signals; 17 and 18 are C
This is a contact output device that converts digital signals from the PUs 5 and 6 into relay drive signals to operate or deactivate output contacts.

また、5は2重化された片系CPU (CPU−A系)
であシ、接点入力装置3からの制御入力信号を入力し、
演算処理後接点出力装置17に出力する。同様に6は2
重化されたもう片系のCPU (CPU −B系)であ
り、接点入力装置4からの制御入力値を読み取り演算処
理後、接点出力装置18に出力する。
In addition, 5 is a duplicated single system CPU (CPU-A system)
input the control input signal from the contact input device 3,
After the arithmetic processing, it is output to the contact output device 17. Similarly, 6 is 2
This is the other CPU (CPU-B system) that is duplicated, and reads the control input value from the contact input device 4, performs arithmetic processing, and outputs it to the contact output device 18.

上記CPU −A系5及びCPU −B系6の故障検出
信号は夫々接点出力装置17.18の強制間入力端子に
入力するよう接続されている。
The failure detection signals of the CPU-A system 5 and CPU-B system 6 are connected to the forced input terminals of the contact output devices 17 and 18, respectively.

第3図に接点出力装置17,18の構成を示す。FIG. 3 shows the configuration of the contact output devices 17 and 18.

但し、接点出力装置18は全く同一構成のため省略した
。接点出力装置17.18は強制間入力信号がOFFの
場合に、CPUからのディジタル出力信号に従ってリレ
ーRYが0N10FF動作できるよう構成されており、
強制間入力信号がONの場合はCPUからのディジタル
出力信号にかかわらず、リレーRYを強制的にOF’F
 (不動作)させる機能を有する。上記接点出力装置1
7.18の出力は第2図に示す構成図のORゲート20
を介してプロセス1に出力される。
However, the contact output device 18 is omitted because it has exactly the same configuration. The contact output devices 17 and 18 are configured so that when the forced input signal is OFF, the relay RY can operate 0N10FF according to the digital output signal from the CPU.
If the forced input signal is ON, relay RY is forced OFF'F regardless of the digital output signal from the CPU.
(inoperable). The above contact output device 1
7. The output of 18 is the OR gate 20 of the block diagram shown in FIG.
is output to process 1 via .

CPU −A系5は接点入力装置3を介して読み取った
プロセスlからの制御入力信号値に基づいて制御演算を
行ない、その演算結果を接点出力装置17を介してOR
ゲート20に伝える。また、CPU−B系6も上記CP
U −A系5同様に接点入力装置4を介して読み取った
プロセス1からの制御入力信号値に基づいて制御演算を
行ない演算結果を接点出力装置18を介してORゲート
20に伝える。上記CPU −A系5、CPU −B系
6は全く同じ演算を行なっているため、CPUが両系と
もの正常である限シ、その演算結果は全く等しい。
The CPU-A system 5 performs control calculations based on the control input signal value from the process l read through the contact input device 3, and ORs the calculation results through the contact output device 17.
Inform Gate 20. In addition, the CPU-B system 6 is also connected to the above CP.
Similarly to the U-A system 5, control calculations are performed based on the control input signal value from the process 1 read via the contact input device 4, and the calculation results are transmitted to the OR gate 20 via the contact output device 18. Since the CPU-A system 5 and CPU-B system 6 perform exactly the same calculations, the results of their calculations are exactly the same as long as both CPUs are normal.

一方、CPU −A系5、CPU −B系6はともに常
に自己診断処理を行なっておシ、異常が検出されれば夫
々CPU−A糸故障信号、CPU −B糸故障信号をO
Nにする。上記故障信号は夫々接点出力装置17.18
の強制開信号の入力端子に接続しているため、CPU 
−A系5に故障が検出されれば接点出力装置17の出力
信号がCPU −A系5のディジタル出力値にかかわら
ず強制的にOFF (開)となり、同様にCPU −B
系に故障が検出されれば接点出力装置18の出力信号が
強制的K OFF (開)となる。
On the other hand, both the CPU-A system 5 and the CPU-B system 6 constantly perform self-diagnosis processing, and if an abnormality is detected, they output a CPU-A yarn failure signal and a CPU-B yarn failure signal, respectively.
Set it to N. The above fault signals are output from contact output devices 17 and 18 respectively.
Since it is connected to the forced open signal input terminal of
If a failure is detected in the -A system 5, the output signal of the contact output device 17 will be forcibly turned OFF (open) regardless of the digital output value of the CPU-A system 5, and the CPU-B
If a failure is detected in the system, the output signal of the contact output device 18 is forced to K OFF (open).

従ってORゲート20の出力状態は下肥のようになる。Therefore, the output state of the OR gate 20 becomes like manure.

i) CPU−A系5、CPU −B系6が共に正常で
あるときCPU −A系5、CPU−B系6は共に正常
であり、その演算結果は全く等しいため、両系の演算結
果が出力される。
i) When CPU-A system 5 and CPU-B system 6 are both normal, CPU-A system 5 and CPU-B system 6 are both normal, and their calculation results are completely equal, so the calculation results of both systems are Output.

ii )CPU −A系5のみ異常であるとき接点出力
装置17の出力がOFFとなるため、CPU −B系6
の演算結果のみが出力される。
ii) When only the CPU-A system 5 is abnormal, the output of the contact output device 17 is turned OFF, so the CPU-B system 6
Only the result of the calculation is output.

1ii) CPU −B系6のみ異常であるとき、接点
出力装置18の出力がOFFとなるため、CPU−A系
5の演算結果のみが出力される。
1ii) When only the CPU-B system 6 is abnormal, the output of the contact output device 18 is turned off, so only the calculation result of the CPU-A system 5 is output.

iV) CPU−A系5、CPU −B系6がともに異
常であるとき、接点出力装置17,18の出力がともに
OFFとなるため、ORゲート20の出力もOFFとな
シ、プロセスlは制御出力がOFFとなるため現状維持
される。
iV) When both the CPU-A system 5 and the CPU-B system 6 are abnormal, the outputs of the contact output devices 17 and 18 are both OFF, so the output of the OR gate 20 is also OFF, and the process l is not controlled. Since the output is turned off, the current status is maintained.

また、上記実施例においてORゲート20をワイアード
OR回路(第4図参照)で構成することによ、9ORゲ
ート20は信号線の結紐だけで構成できるため、新たに
ハードウェアを追加する必要はなく経済的である。
Furthermore, in the above embodiment, by configuring the OR gate 20 with a wired OR circuit (see FIG. 4), the 9OR gate 20 can be configured only by tying the signal lines, so there is no need to add new hardware. It is very economical.

なお上記実施例ではCPU 5 、6を切換える場合に
ついて示したが、手動操作回路30への切換えであって
もよく、第5図に示すようにORゲート20の構成を手
動操作回路30から入力可能にゲートを設けた構成とす
ることにょシ手動操作回路30への切換えも容易に行な
えるようになシ、上記実施例と同様の効果を奏する。
Although the above embodiment shows the case where the CPUs 5 and 6 are switched, switching to the manual operation circuit 30 may also be possible, and the configuration of the OR gate 20 can be input from the manual operation circuit 30 as shown in FIG. By providing a gate in the configuration, switching to the manual operation circuit 30 can be easily performed, and the same effects as in the above embodiment can be obtained.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば接点出力装置にCPU
が異常であるときは強制的に出力をOFFとする機能を
付加し、CPUの切換をORゲートで行なうように構成
したので、装置が安価にでき、また信頼性の高い冗長化
ディジタル式制御装置が得られるという効果がある。
As described above, according to the present invention, the CPU is connected to the contact output device.
We added a function to forcibly turn off the output when there is an abnormality, and configured the CPU to switch using an OR gate, making the device inexpensive and highly reliable redundant digital control device. This has the effect that it can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の冗長化ディジタル式制御装置を示す構成
図、第2図はこの発明の一実施例による冗長化ディジタ
ル式制御装置を示す構成図、第3図は第2図の接点出力
装置部分を示す構成図、第4図は第2図のORゲート部
分を示す構成図、第5図はこの発明の他の実施例による
手動操作回路を含んだ冗長化ディジタル式制御装置を示
す構成図である。 l・・・プロセス、2・・・制御装置、5,6・・・C
PU 。 17.18・・・接点出力装置、20・・・ORゲート
。 なお、図中、同一符号は同一、又は相当部分を示す。 特許出願人 三菱電機株式会社
Fig. 1 is a block diagram showing a conventional redundant digital control device, Fig. 2 is a block diagram showing a redundant digital control device according to an embodiment of the present invention, and Fig. 3 is a contact output device of Fig. 2. FIG. 4 is a configuration diagram showing the OR gate portion of FIG. 2; FIG. 5 is a configuration diagram showing a redundant digital control device including a manual operation circuit according to another embodiment of the present invention. It is. l...process, 2...control device, 5, 6...C
P.U. 17.18...Contact output device, 20...OR gate. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant Mitsubishi Electric Corporation

Claims (1)

【特許請求の範囲】[Claims] 中央演算処理ユニットが多重化された冗長化ディジタル
式制御装置において、上記各中央演算処理ユニットが正
常な場合は該各中央演算処理ユニットが演算処理した制
御出力を出力し、異常な場合は該制御出力を不出力にす
る接点出力装置と、上記各接点出力装置の論理和信号を
プロセスへ供給するORゲートとを備えたことを特徴と
する冗長化ディジタル式制御装置。
In a redundant digital control device in which central processing units are multiplexed, when each central processing unit is normal, it outputs the control output processed by each central processing unit, and when it is abnormal, it outputs the control output 1. A redundant digital control device comprising: a contact output device for disabling output; and an OR gate for supplying a logical sum signal of each of the contact output devices to a process.
JP59045715A 1984-03-12 1984-03-12 Redundant digital controller Pending JPS60191339A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59045715A JPS60191339A (en) 1984-03-12 1984-03-12 Redundant digital controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59045715A JPS60191339A (en) 1984-03-12 1984-03-12 Redundant digital controller

Publications (1)

Publication Number Publication Date
JPS60191339A true JPS60191339A (en) 1985-09-28

Family

ID=12727044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59045715A Pending JPS60191339A (en) 1984-03-12 1984-03-12 Redundant digital controller

Country Status (1)

Country Link
JP (1) JPS60191339A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106444354A (en) * 2015-08-11 2017-02-22 南京理工大学 Double-CPU redundant controller
JP2021033600A (en) * 2019-08-23 2021-03-01 三菱電機株式会社 Digital output device
JP7158551B1 (en) * 2021-10-15 2022-10-21 株式会社京三製作所 Contact output device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106444354A (en) * 2015-08-11 2017-02-22 南京理工大学 Double-CPU redundant controller
JP2021033600A (en) * 2019-08-23 2021-03-01 三菱電機株式会社 Digital output device
JP7158551B1 (en) * 2021-10-15 2022-10-21 株式会社京三製作所 Contact output device

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