JPS58203561A - Controlling device of external storage - Google Patents

Controlling device of external storage

Info

Publication number
JPS58203561A
JPS58203561A JP57084745A JP8474582A JPS58203561A JP S58203561 A JPS58203561 A JP S58203561A JP 57084745 A JP57084745 A JP 57084745A JP 8474582 A JP8474582 A JP 8474582A JP S58203561 A JPS58203561 A JP S58203561A
Authority
JP
Japan
Prior art keywords
external storage
circuit
central processing
cpu1
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57084745A
Other languages
Japanese (ja)
Inventor
Haruo Kazami
風見 晴雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57084745A priority Critical patent/JPS58203561A/en
Publication of JPS58203561A publication Critical patent/JPS58203561A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To separate a defective bus forcibly from an external storage controlling device to be coupled with plural CPUs through different data buses and to switch the controlling device to the other system by providing the controlling device with a bus fault checking means in each bus system independently. CONSTITUTION:Regarding that a CPU1 is a current system and a CPU2 is an auxiliary system, data are transferred between the CPU1 and an external storage device 13 through the external storage controlling device 24. When an error is detected by a parity check circuit 3 in the device 24, an error latch circuit 5 is set up. The output of the circuit 5 is sent to the CPU1 through a signal line 18 and the CPU1 recognizes the generation of a fault in the data bus system and returns a response signal through a signal line 19. As the result, the output of an AND circuit 8 is turned to ''0'', the AND condition of an AND circuit 10 is not satisfied and the external storage device 13 is separated from the CPU1. If the error is not recovered by retrial, a selecting circuit 7 turns a signal line 22 to ''0'' and a signal line 23 to ''1'', so that the condition of an AND circuit 11 is satisfied and the external storage device 13 is coupled with the CPU2.

Description

【発明の詳細な説明】 発明の対象 本発明は、電子d[算機システムにおける外部記憶制御
装置に係り、特に、二重化システムζ:おける系の切り
替え制御を容易に行う外部記憶制御装置に関する。
DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to an external storage control device in an electronic computer system, and more particularly to an external storage control device that easily performs system switching control in a redundant system ζ.

従来技術 今日、電子計算機システムは、外部記憶装置の大容門化
、高速化と共に、システムの高度の信頼性が蒙求されて
いる。この為、一般1大形の計算機システムではシステ
ムの二重化が行なわれており、一台の中央処理装置で障
害が発生してダウンしても、他の中央処理装置へ切り替
えることにより、全体のシステムダウンを防いでいる。
BACKGROUND OF THE INVENTION Today, electronic computer systems are required to have larger capacity and faster external storage devices, as well as higher system reliability. For this reason, most large-scale computer systems have system duplication, and even if one central processing unit fails and goes down, the entire system can be restored by switching to another central processing unit. Prevents you from going down.

一方、外部記憶装置の障害については、一般に一つのジ
ョブを実行しているとき、そのジョブζ=関するエリヤ
において発生するから、そのジョブのキャンセルにはな
るが、システムダウンも一発展することは少ない。
On the other hand, a failure in an external storage device generally occurs in an area related to the job ζ when a single job is being executed, so although the job may be canceled, it is unlikely that the system will go down. .

さて、中央処理装置(=おいである障害が発生して他の
系への切り替えが必要な場合、以下の手順が必要となる
Now, if a failure occurs in the central processing unit and it is necessary to switch to another system, the following steps are required.

(1)  現在結合されている中央処理装置と外部記憶
制御#c*とを切り離す。
(1) Disconnect the currently connected central processing unit and external storage control #c*.

(21他の糸の中央処理装置と外部記憶制御装置との結
合を行う。
(21) Connects the central processing unit of another thread and the external storage control unit.

ここで、(1)の切り離しが出来ればよいが、出来なけ
れば、(2)の結合も出来ない。従って、障害によって
切り離し不能になれば、二重化システムにおいてもシス
テムダウンはまぬがれないことになる。
Here, it is good if (1) can be separated, but if it is not possible, (2) cannot be combined. Therefore, even in a redundant system, system failure is inevitable if a failure makes it impossible to disconnect.

そこで、最近の技術においては、中央処理装置の障害の
場合には、その信号を独立のラインを設けて外部記憶制
御装置(二速ること(二より、この信号をトリガーにし
てハードウェアにて強制切り離しを行なっている。とこ
ろが、ケーブル接続口、ドライバ、レシーバ等のデータ
バス系の障害においては、中央処理装置側で検出するこ
とが出来ず、又、外部記憶装置の制御する部分にはまっ
たく支障がないにもかかわらず、切り離し不能状態が発
生する。これは以下の理由による。
Therefore, in recent technology, in the event of a failure of the central processing unit, an independent line is provided to transmit the signal to the external storage controller (two-speed). However, failures in data bus systems such as cable connections, drivers, and receivers cannot be detected by the central processing unit, and the parts controlled by external storage devices are not affected at all. A non-separable state occurs even though there are no problems.This is due to the following reasons.

(1)  中央処理装置からプログラムによる切り離し
コマンド発行によって切り離しを実行しようとしても、
障害の性質上、外部記憶制御装置への伝達が不能になる
(1) Even if you try to perform disconnection by issuing a programmatic disconnection command from the central processing unit,
Due to the nature of the failure, communication to the external storage controller is impossible.

(2)  前記障害が外部記憶制御装置又は外部記憶装
置との障害の切り分けが出来ないため、事実上、系の切
り賛えも出来ない。
(2) Since it is not possible to isolate whether the failure is related to the external storage control device or the external storage device, it is virtually impossible to treat the system.

このように、従来は二重化システムにおいても、データ
バス糸の障害が発生すればシステムダウンに発展すると
いう非常に大きな問題があった。
As described above, even in duplex systems, there was a very serious problem in the past in that if a failure occurred in the data bus thread, the system would go down.

発明の目的 本発明の目的は、データバス系の障害が発生しても切り
離しができ、他系への切り替えを可能とする外部記憶制
御装置を提供することにある。
OBJECTS OF THE INVENTION An object of the present invention is to provide an external storage control device that can be disconnected even if a failure occurs in the data bus system and switch to another system.

本発明は外部記憶制御装置(=、データバス系の障害に
対して系ごとの独立のチェック機能を持たせ、障害が発
生したとき、その旨を中央処理装置に送り、その応答信
号により結合状態を強制的に切り離し、これにより他系
への切り替えを容易にするものである。
The present invention provides an independent check function for failures in the external storage control device (= data bus system), and when a failure occurs, it sends a notification to that effect to the central processing unit, and the connection state is determined by a response signal. This forcibly disconnects the system, thereby making it easier to switch to another system.

発明の実施例 図は本発明の一実施例で、破線%内が本発明にかかる外
部記憶制御装置を示す。外部記憶制御回路誇ま外部記憶
制御回路12と中央処理装置l又は2のどちらを選択す
るかの制御を行う選択回路7とこれに付随した回路群か
らなる。
Embodiment of the Invention The figure shows an embodiment of the invention, and the area within the broken line % indicates an external storage control device according to the invention. The external storage control circuit consists of an external storage control circuit 12, a selection circuit 7 that controls which of the central processing units 1 and 2 is selected, and a group of associated circuits.

今、中央処理装置llの側を現用・系、中央処理装置2
の側を予備系とし、当該外部記憶装置2I41Iま中央
処理装置lと結合状態にあるとする。この場合、選択回
路7は信号線22を°l”、信号線路を101とする。
Now, the central processing unit ll side is the current system, central processing unit 2.
It is assumed that the external storage device 2I41I is connected to the central processing unit 1. In this case, the selection circuit 7 sets the signal line 22 to °l'' and the signal line to 101.

これにより、AND回路旬のAND条件が成立して(後
述するように、通常、AND回路8の出力は11”であ
る)、データバス14Ib1中央処理装置lとの結合状
態が決定する。この結合状態においては、当該外部記憶
装置装置蝕を介し、中央処理装置lと外部記憶装置18
の間でデータバス14.16によるデータ転送が村われ
る。
As a result, the AND condition of the AND circuit is satisfied (as described later, the output of the AND circuit 8 is normally 11"), and the connection state of the data bus 14Ib1 with the central processing unit 1 is determined. This connection In the state, the central processing unit 1 and the external storage device 18 are connected through the external storage device 18.
Data transfer via data buses 14 and 16 is performed between the two.

さて、外部記憶装置油ま、中央処理装置lから送出され
るデータをデータバス14によりパリティチェック回路
8に人力して、パリティチェックを行う。パリティチェ
ック回路8でエラーを検出すると、エラーラッチ回路5
をセットする。エラーラッチ回路5の出力は信号線18
により中央処理装置lに送られ、これにより中央処理装
置lはデータバス系の障害が発生したことを認識し、信
号線19を通して応答信号を返送してくる。その結果、
AND回路8の出力はO″となるため(該AND回路8
の出力にある1。」はインバータを示す)、AND回路
lOのAND条件が成立しなくなり、中央処理装置1と
の切り離しが達成する。なお、エラーラッチ回路5は、
中央処理装置1からの応答信号でリセットされる。これ
により、系の移し替えを行わずに、一つの系だけのりト
ライも可能になる。リトライによってもエラーが回復し
ない場合、選択回路7は信号線22を@θ″とし、かわ
り(二信号llm28を“l″としてAND回路11の
粂件をとり、中央処理装置2と結合状態にする。
Now, data sent from the external storage device or central processing unit 1 is manually input to the parity check circuit 8 via the data bus 14 to perform a parity check. When the parity check circuit 8 detects an error, the error latch circuit 5
Set. The output of the error latch circuit 5 is the signal line 18
The signal is then sent to the central processing unit l, which recognizes that a failure has occurred in the data bus system and sends back a response signal through the signal line 19. the result,
Since the output of the AND circuit 8 becomes O'' (the AND circuit 8
1 in the output of. '' indicates an inverter), the AND condition of the AND circuit IO no longer holds, and the disconnection from the central processing unit 1 is achieved. Note that the error latch circuit 5 is
It is reset by a response signal from the central processing unit 1. This makes it possible to try using only one system without changing systems. If the error is not recovered even after retrying, the selection circuit 7 sets the signal line 22 to @θ'' and instead sets the AND circuit 11 to the two-signal llm28 to "l", and connects it to the central processing unit 2. .

従来技術においては、パリティチェックは外部記憶Th
1J111回路12の前で行なっており、故障の部位の
判断が出来ず、従って糸の切り替えも不可能であった。
In the conventional technology, parity check is performed using external storage Th.
Since this was done in front of the 1J111 circuit 12, it was not possible to determine the location of the failure, and therefore it was impossible to switch the yarn.

父、独立に設けたとしても、中央処理装置が、認識出来
なければ、やはり切り替えは出来ない。これに対し、本
発明ではパリティチェックを系ごとに独立に持たせ、か
つ中央処理装置との独立の応答ラインを設けることによ
り、切り替えを可能としたものである。
Father, even if it is installed independently, if the central processing unit cannot recognize it, it will still not be possible to switch. In contrast, in the present invention, switching is made possible by providing a parity check independently for each system and by providing a response line independent of the central processing unit.

以上、外部記憶制御装置24が中央処理装置lと結合さ
れている場合を例に説明したが、中央処理装[2と結合
状態にある場合の動作も全く同様である。
Although the case where the external storage control device 24 is coupled to the central processing unit 1 has been described above, the operation is exactly the same when the external storage control device 24 is coupled to the central processing unit [2].

発明の効果 本発明によれば、データバス系障害が発生しても、糸の
切り離しが確実かつ容易に出来るので、糸の切り誉えが
可能となる。これにより、上記障害が発生してもシステ
ムダウンを免かれ、システムの信頼性を上げ、障害発生
時のダメージを軽減する効果がある。
Effects of the Invention According to the present invention, even if a failure occurs in the data bus system, the thread can be cut off reliably and easily, so that the thread can be cut properly. This prevents the system from going down even if the above-mentioned failure occurs, increases system reliability, and has the effect of reducing damage when a failure occurs.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明に係る外部記憶制御装置の一実施例の構成図
である。 1、 2・・・中央処理itt、8,4・・・パリティ
チェ1′:
The figure is a configuration diagram of an embodiment of an external storage control device according to the present invention. 1, 2... central processing itt, 8, 4... parity check 1':

Claims (1)

【特許請求の範囲】[Claims] (1)複数の中央処理装置とそれぞれ異なったデータバ
ス系で結合され、該複数の中央処理装置と外部記憶装置
との間のデータ転送制御を行う外部記憶制御装置におい
て、前記データバス系の障害;=対して糸ごとの独立の
チェック手段を設け、障害が亀生したとき、当該データ
バス系に結合されている中央処理#cr1tに連結し、
該中央処理装置からの応答信号により当該データバス系
の結合状態を強制的に切り離すことを%像とする外部記
憶制御装置。
(1) In an external storage control device that is connected to a plurality of central processing units through different data bus systems and controls data transfer between the plurality of central processing units and an external storage device, a failure in the data bus system ;= An independent check means is provided for each thread, and when a failure persists, it is connected to the central processing #cr1t connected to the data bus system,
An external storage control device whose purpose is to forcibly disconnect the connection state of the data bus system by a response signal from the central processing unit.
JP57084745A 1982-05-21 1982-05-21 Controlling device of external storage Pending JPS58203561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57084745A JPS58203561A (en) 1982-05-21 1982-05-21 Controlling device of external storage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57084745A JPS58203561A (en) 1982-05-21 1982-05-21 Controlling device of external storage

Publications (1)

Publication Number Publication Date
JPS58203561A true JPS58203561A (en) 1983-11-28

Family

ID=13839222

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57084745A Pending JPS58203561A (en) 1982-05-21 1982-05-21 Controlling device of external storage

Country Status (1)

Country Link
JP (1) JPS58203561A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134846A (en) * 1984-12-04 1986-06-21 Omron Tateisi Electronics Co Electronic computer system
JPH07200334A (en) * 1993-12-29 1995-08-04 Nec Corp Duplicate synchronization operation system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61134846A (en) * 1984-12-04 1986-06-21 Omron Tateisi Electronics Co Electronic computer system
JPH07200334A (en) * 1993-12-29 1995-08-04 Nec Corp Duplicate synchronization operation system

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