JPH079636B2 - Bus diagnostic device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a bus diagnostic device for inspecting the presence or absence of a fault in a system bus, for example, a dual centralized control including a centralized control device for an active system and a standby system. It is applicable to the system.

[Prior Art] Conventionally, as a bus diagnostic device for monitoring an abnormality of a system bus connecting a controlled device such as a magnetic disk control device controlled by a central control unit (CPU) and the central control device, Japanese Patent Application Laid-Open No. -97763 has been disclosed.

This is because when the central control device fetches data from the controlled device via the bus, it captures the data contents at two different timings based on the control signal corresponding to the data and stores them in the register circuit respectively. The bus is diagnosed when the data contents match or do not match, and a warning is issued to the central control unit when the data do not match.

[Problems to be Solved by the Invention] According to the above-mentioned bus diagnosis device, the advantage that the bus diagnosis can be executed in a normal data transfer cycle, that is, the central control unit takes time for bus diagnosis, is taken. There is no advantage.

However, according to the above-mentioned bus diagnostic device, since it is realized by a hardware configuration such as a delay circuit for producing different latch timings and a comparator for discriminating coincidence / non-coincidence, different circuit elements (integrated circuits) are provided for each function. including)
Therefore, many circuit elements are actually used, and there is a problem that the area occupied on the printed wiring board becomes large. Moreover, since the diagnostic device configuration is required for each bus with the controlled device, the above-mentioned problem is particularly serious in this respect.

In the dual centralized control system, the central control units of the active system and the standby system are connected via both system connection buses, but when the above-mentioned bus diagnostic device is provided for the bus of the active system and the standby system. Cannot diagnose both system connection buses,
Even if a diagnostic device is installed on this bus in order to diagnose both system connection buses, when both system connection buses are accessed, the operating or standby buses are also accessed. Or, it is not possible to detect which of the active bus (or the standby bus) has failed.

The present invention has been made in consideration of the above points, and an object of the present invention is to provide a bus diagnostic apparatus suitable for being applied to a system having a small hardware configuration and a wide variety of buses.

[Means for Solving the Problem] In order to solve the problem, according to the present invention, an address on an address bus connecting a central control device and a controlled device is taken in and a control signal is sent when the address is predetermined. An address decode circuit for outputting, and a register circuit for outputting data to the data bus or taking in and storing the data on the data bus according to a control signal from the address decode circuit and a control signal from the central control unit. Prepared

Then, the central control unit causes the address bus and the data bus to output a predetermined address and data, causes the register circuit to store the output data, and then outputs the predetermined address to the address bus and stores the data in the register circuit. The present data is output to the data bus and fetched, and the fetched data is compared with the data output to be stored in the register circuit to diagnose the data bus.

[Operation] In the bus diagnostic device of the present invention, the central controller once outputs diagnostic data, stores the data in the register circuit, reads the stored data from the register circuit, and then fetches the data. At least the data bus is diagnosed by determining whether or not the data output from the central control unit and the data returned from the register circuit match.

At this time, writing or reading of data to or from the register circuit is controlled by giving an address to the address code circuit.

[Embodiment] An embodiment of the present invention will be described in detail below with reference to the drawings.

Here, FIG. 1 is a block diagram showing the configuration of the bus diagnostic apparatus of this embodiment, FIG. 2 is a flowchart showing the processing in the bus diagnostic mode executed by the central control unit, and FIG. It is a block diagram with which explanation of an effect at the time of applying a bus diagnostic device to a duplication central control system is given.

In FIG. 1, from the central control unit 10, the address bus
11 and the data bus 12 are extended, a plurality of control signal lines not shown are extended,
The address bus 11 and the data bus 12 are connected to a controlled device (not shown).

In the case of this embodiment, the address bus 11 and the data bus 12
Are connected to the bus termination package 13 in addition to the controlled devices. In the bus termination package 13, the address bus 11 is connected to the address decoding circuit 14.
The address decoding circuit 14 outputs a response signal to the central control unit 10 via the response signal line L1 when the address on the address bus 11 has a predetermined value, and
An enable signal is applied to the register circuit 15 via the control signal line L2.

A write / read signal for instructing the register circuit 15 to write or read is given from the central controller 10 to the register circuit 15 through the control signal line L3.

The register circuit 15 is connected to a data bus 12 that connects the central control device 10 and a controlled device (not shown). The register circuit 15 takes in and stores the data on the data bus 12 and stores the stored data in the data bus 12. Output to above.

Next, the bus diagnosis processing executed by the central controller 10 will be described in detail with reference to FIG.

The central controller 10 starts the bus diagnostic processing program shown in FIG. 2 at predetermined intervals, first outputs the first address determined for diagnosis to the address bus 11, and also determines the first address determined for diagnosis. The selected data is output to the data bus 12, and then the write mode is instructed to the register circuit 15 (steps 100 to 102).

At this time, the address decoding circuit 14 causes the central controller 10 to
To the register circuit 15 and outputs a write enable signal to the register circuit 15. As a result, the register circuit 15 stores the data output by the central controller 10 for diagnosis.

The central controller 10 determines whether or not the response signal is given from the address decoding circuit 14 within a predetermined time from the time when the write mode is instructed to the register circuit 15, and the response signal is received within the predetermined time. If not given, it is determined that a failure has occurred in the address bus 11 and a warning is issued to that effect to terminate the bus diagnostic processing (step 10).
3, 104).

On the other hand, when the response signal is given, the central control unit 10 outputs the second address for the address decoding circuit 14 to the address bus 11, and thereafter instructs the register circuit 15 to the read mode (steps 105 and 106). ).

At this time, the address decoding circuit 14 causes the central controller 10 to
To the register circuit 15 and outputs an output enable signal to the register circuit 15. As a result, the register circuit 15 outputs the stored data to the data bus 12.

When instructing the read mode to the register circuit 15 as described above, the central control unit 10 determines whether or not a response signal is given from the address decoding circuit 14 within a predetermined time, and the response signal within the predetermined time. Is not given,
It is determined that a failure has occurred in the address bus 11 and a warning is issued to that effect to terminate the bus diagnostic processing (steps 107 and 104).

On the other hand, when the response signal is given, the central control unit 10 takes in the data on the data bus 12, and the taken-in data and the data output to the data bus 12 in step 101 described above (the central control unit 10 has a built-in register). (This data is stored in the circuit) It is discriminated whether or not it matches (step)
108, 109).

As a result, when it is determined that they match, a series of bus diagnosis processing is ended. On the other hand, if it is determined that they do not match,
It is determined that a fault has occurred in the data bus 12, a warning is issued to that effect, and the bus diagnostic process is terminated (step 110).

In this way, the data is once written to the register circuit 15 for bus diagnosis, the data is taken out from the register circuit 15 and compared with the data to be written to diagnose the data bus 12. Of the address bus 11 by causing the address decoding circuit 14 to generate an enable signal for access operation to the CPU, and causing the central controller 10 to report that the address has been taken in almost in synchronization with the enable signal. Is also doing.

Therefore, according to the above-described embodiment, the circuits necessary for bus diagnosis are the address decoding circuit 14 and the register circuit 15.
Therefore, the hardware configuration may be smaller than that of a conventional delay circuit or comparator. In practice, in order to realize a decoding circuit or register circuit, it is often possible to use a common IC chip as compared with the case where a delay circuit or a comparator is realized. Therefore, the number of circuit elements can be small, and the occupied area can be reduced.

Further, the bus diagnostic device according to the above-mentioned embodiment does not need to be separately provided for each bus to be diagnosed. This is because it is possible to detect faults at not only one location but also a plurality of locations depending on how to use this bus diagnostic device.

FIG. 3 is provided for explaining the effect when the bus diagnostic device according to the above-mentioned embodiment is applied to the duplicated central control system.

In FIG. 3, the duplicated central control system 20 comprises two systems 21 consisting of a central control device, controlled devices and bus connecting devices.
And 22, one of which is an active system and the other system is a standby system. Hereinafter, for convenience of explanation, the system 21 will be referred to as an active system, and the system 22 will be referred to as a standby system.

The central controller 21A in the operation system 21 is the system bus 21D.
The controlled device 21B is controlled via the. On the other hand, the central control device 22A in the standby system 22 controls the controlled device 22B via the system bus 22D when the system 22 is switched to the operating system.

In this case, if the controlled devices 21A and 22B are auxiliary storage devices so that the operation system 21 and the standby system 22 can be smoothly switched, the central control unit 21A of the operation system 21 is used.
The information from the controlled device 21B to the controlled device 21B is also given from the central control device 21A to the controlled device 22B of the standby system 22. But,
In order to prevent malfunction, the central control device 21A is given only the data from the controlled device 21B and not the data from the controlled device 22B of the standby system 22.

Therefore, each system is provided with bus connection devices 21C and 22C for controlling connection with the bus of the other system, and both system connection buses 23 are connected between these bus connection devices 21C and 22C.

These bus connecting devices 21C and 22C are respectively provided with the address decoding circuit and the register circuit in the above-mentioned bus diagnostic device. Note that different addresses are assigned to the address decode circuits in the bus connection device 21C and the address decode circuits in the bus connection device 22C.

The central controller 21A of the operation system 21 is the system bus 21D of its own system.
When diagnosing, make the system bus 21D and the system common bus 23 separated by the bus connection device 21C,
The bus diagnosis process as described above is executed for the address decode circuit and the register circuit provided in the bus connection device 21C.

Further, when the central control unit 21A diagnoses the system connection bus 23, the system bus 22D of the standby system 22 is replaced by the system common bus 2
In the state of being separated from 3, the above-mentioned bus diagnostic processing is executed for the address decoding circuit and the register circuit provided in the bus connecting device 22C. At this time, the effects of both the system bus 21D of the active system and the connection bus 23 of both systems are reflected in the diagnosis result, but as described above, the system bus 21D alone is diagnosed and the result is obtained. By referring to the result, the both-system connection bus 23 can be diagnosed.

When the central controller 21A of the operating system 21 diagnoses the system bus 22D of the standby system 22, the central controller 21A
Is the system bus 21 for the bus connection devices 21C and 22C.
After connecting D, both system connection bus 23, system bus 22D,
The bus diagnosis processing as described above is executed for the address decode circuit and the register circuit provided in the bus connection device 22C. At this time, the influence of the active system bus 21D, the dual system connection bus 23, and the standby system bus 22D is reflected in the diagnosis result.
When the diagnosis is performed in advance on 21D and the two-system connection bus 23 and the result is obtained, the system bus 22D can be diagnosed by referring to the result.

When the central control unit 22A of the standby system 22 diagnoses each bus, the same operation as described above is performed.

As described above, the bus diagnostic device having the configuration of FIG.
When applied to the redundant central control system, it is possible to make a diagnosis for each bus, that is, for which fault location.

In the above description, the case where the bus diagnostic device of the present invention is applied to the duplicated central control system has been shown, but it can be appropriately applied to other information processing systems as necessary.

Further, in the above embodiment, the address decode circuit 14 outputs the enable signal for the register circuit 15, but the central controller 10 may output the response signal after receiving the response signal.

Further, in the above-described embodiment, the central control unit 10 outputs the write / read signal to the register circuit 15, but the address decoding circuit 14 may output it. That is, the write / read signal may be output first before the address decoding circuit 14 outputs the enable signal.

Further, in the above description, the present invention is applied to the duplicated central control system in which the bus connection devices 21C and 22C can control the system bus of both systems and the system connection buses by separating them from each other.
These buses may be applied to a central control system in which the bus connection device cannot be disconnected. Also in this case, a failure location can be diagnosed by providing a pair of the address decode circuit and the register circuit in each part.

[Effects of the Invention] As described above, according to the present invention, when the bus diagnostic mode is entered, the central control unit outputs the data to the data bus and outputs the address to the address bus, so that the data is stored in the register circuit. Once stored, the address is output to the address bus to read out and drive the above register circuit to output data from the register circuit, and the central controller compares the data before and after stored in the register circuit and Since the diagnosis is made, the hardware-required configuration may be small, and the overall configuration can be made compact.

Further, by appropriately changing the address for the address decoding circuit, it is possible to change the diagnosis location, and it is possible to identify the failure location even when applied to an information processing system in which a plurality of buses are appropriately connected and controlled. Will increase.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bus diagnostic apparatus according to the present invention, FIG. 2 is a flow chart showing processing executed by the central control unit in the bus diagnostic mode, and FIG. 3 is a bus diagnostic apparatus of the above embodiment. It is a block diagram which shows the structure of the duplicated central control system to which is applied. 10 ... Central control unit, 11 ... Address bus, 12 ... Data bus, 14 ... Address decoding circuit, 15 ... Register circuit.

Claims (1)

[Claims] 1. A bus diagnostic device for diagnosing a state of an address bus and a data bus connecting a central control device and a controlled device controlled by the central control device, comprising: the central control device and the controlled device. The address decode circuit which takes in the address on the address bus connecting the two and outputs the first control signal and the response signal according to the address, and the data on the data bus according to the input write / read signal The mode of storing or outputting the stored data to the data bus is selected,
A register circuit for fetching and storing the data on the data bus in response to the first control signal from the address decoding circuit or for outputting the stored data to the data bus; The address bus is diagnosed by inputting the response signal, and the data stored in the register circuit is compared with the data output for storing in the register circuit according to the diagnosis result of the address bus. A bus diagnostic device characterized in that it diagnoses a data bus.