JPH03268149A - Memory fault detection system - Google Patents

Abstract

PURPOSE:To detect a memory fault during a test of the operation of an electronic device by outputting only read data from a 2nd memory part to a common bus and storing unmatching data in a temporary storage circuit when a data matching monitor means detects the unmatching. CONSTITUTION:A memory circuit 1 which constitutes part of the electronic device has a 1st memory part 1 where data are written and read through the common bus connected to a processor 3, and a memory monitor circuit 2 which monitors the operation of the memory circuit 1 has a 2nd memory part 21. In the write cycle of the processor 3, the same data is written in the 1st and 2nd memory parts 21. In the read cycle of the processor 3, only when the data unmatching monitor means 23 detects the unmatching, the read data from the 2nd memory part 21 is outputted to the common bus 4 and the unmatching data and address are stored in the temporary storage circuit 24.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for detecting memory faults in an electronic device, an object of the present invention is to provide a memory fault detection method capable of detecting a memory fault during execution of an operation test of an electronic device. comprising a first memory section and a second memory section connected to a processor via a common bus, wherein data is read from the first memory section and the second memory section, respectively, during a read cycle of the processor. a data matching monitoring means for matching data, and in a write cycle of the processor,
When the same data is simultaneously written to the first memory section and the second memory section, and a mismatch is detected by the data coincidence monitoring means in the read cycle of the processor, the second memory section is written to the common lot. It is configured to output only read data from the memory section and store the mismatched data and address in a temporary storage circuit.

[Industrial application field]

The present invention relates to a method for detecting memory faults in electronic devices.

In recent years, the integration density, lower power consumption, and higher speed of semiconductor memories have progressed significantly, and as a result, semiconductor memory users are also rapidly developing new products that incorporate these high-performance semiconductor memories. It is being advanced.

Under such a new product development environment, it is not uncommon for a product incorporating a high-performance memory under development to be designed in anticipation of completion.

However, in many cases, the detailed usage conditions for such new memories under development are not clear, or evaluations have not yet been completed to determine whether the design goals and actual performance completely match. When a new memory is designed, peripheral hardware and software are often also newly designed, making evaluation testing of products using newly developed semiconductor memory complicated. Therefore, when evaluating new products, it is important to efficiently detect failures in the memory circuit portion caused by design errors or initial failures.

When trying to detect a fault in a memory circuit, conventional technology involves writing and reading data to the memory.
Memory testing that compares written data and read data is common, but memory testing takes up a larger proportion of product testing time than when using proven semiconductor memory. becomes. Therefore, even when using such newly developed memory,
There is a need for an efficient fault detection method that can detect memory faults during operation tests of electronic devices using the memory without spending a large amount of time testing individual memories.

[Conventional technology]

FIG. 5 is a configuration diagram of the prior art, showing an example of the configuration of an electronic device, centering on a memory circuit.

In FIG. 5, the memory section 11 in the memory circuit 1 includes an integrated circuit (for example, including built-in related circuits (not shown)).
Assuming that the memory is a newly developed memory that is integrated circuit (IC), a case will be described in which the memory circuit 1 is tested with emphasis on the memory section 11.

In the prior art, when testing the memory function of the memory circuit 1, the processor 3 writes data to the memory section 11 using, for example, a memory test program, and then reads the written data so that both Verify that the memory function is normal by checking that they match.

Data is written to the memory section 11 by the processor 3.
This is executed by specifying an address via the address bus 4a, issuing a write instruction via the control bus 4b, and sending write data to the data bus 4c. First, when a write instruction from the control bus 4b is input to the write/read controller 14, the write/read controller 14 receives the write/read instruction from the control bus 4b.
The read controller 14 instructs the memory unit 11 to select a chip from the C3 line to select a memory chip (not shown) in the memory 11, and then sends a signal from the RW line notifying that writing is to be performed. Furthermore, a signal RD is sent to the HSS driver/receiver 12 from the G line to open the gate of the receiver circuit (details not shown).
A signal notifying that write data is input is sent from the line to put the hash driver/receiver 12 in a state in which data can be written.

Following these, data is sent to the data bus 4c,
At the same time, a write pulse is sent from the WP line to the memory section 11 via the control bus 4b and the write/read controller 14, and the data is written into the memory section 11.

To write multiple pieces of data, repeat the above operations.

To read the data written in the memory section 1, the processor 3 first specifies the address from which the data is to be read into the memory section 11 via the address bus 4a, and a read instruction from the control bus 4b is input to the write/read controller 14. Then, the read l-/read controller 14 issues a chip select instruction to the memory section 11 from the C3 line to select a memory chip. Next, a signal instructing the memory unit 11 to read data is sent from the RW line, and the bus driver/receiver 1
A signal for opening the gate of the driver circuit from the G line and a signal for operating the circuit for outputting the read data from the RD line are sent to the bus driver/receiver 12 to bring the bus driver/receiver 12 into a state where the read data can be sent.

In this way, data is read from the specified address in the memory unit 11, and is sent to the processor 3 via the data bus 4c.
sent to. When reading multiple pieces of data, repeat the second operation.

The processor 3 compares the data previously written by the test program with the data read out, and if they do not match, records the address and data contents (details not shown).

In the conventional technology, it is possible to test the memory circuit 1 as described above, but since the above test is a dedicated test for memory, it takes a lot of time and effort for the memory test. This is the result.

[Problem to be solved by the invention]

In conventional technology, for electronic devices designed using newly developed semiconductor memory at the development stage, tests are conducted on the memory part to confirm that there are no design errors or initial defects. Among the tests for electronic devices, there has been a problem in that memory tests require a great deal of time and effort.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory fault detection method capable of detecting memory faults during execution of an operational test of an electronic device.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, ■ is a memory circuit constituting a part of the electronic device, and the first memory circuit branches from the common path 4 connected to the processor 3.
A memory circuit 2 includes a first memory section 1a to which writing and reading are performed under the control of the processor 3 via an address bus 4a, a control bus 4b, and a data bus 4c; A memory monitoring circuit is added to the electronic device to monitor the operation of the memory circuit 1, and performs writing and reading via a second address bus 4d, a control bus 4e, and a data bus 4f branched from the common path 4. 3 is a processor for controlling the electronic device; 4 is a common hub for transferring data between the electronic device and the memory circuit 1, the memory monitoring circuit 2, etc.; 4a; , 4d is one of the bus lines branched from the common bus 4, and a signal designating an address from the processor 3 to the first and second memory sections 11 and 21 in the memory circuit 1 and the memory monitoring circuit 2. 1st and 2nd sent
The address buses 4b and 4e are also branched from the common path 4, and are connected to first and second controllers I to which write or read control signals are sent from the processor 3 to the first and second memory sections LL21.・Rollhus, 4c
, 4f are similarly branched from the common path 4, and the processor 3 sends data to be written to the first and second memory sections LL21, and the first and second memory sections 1121 store the data. first and second data buses through which data is sent to the processor 3;

11 to 13 are each part in the memory circuit 1, and 11 is a semiconductor (
I'C) A first memory section consisting of a memory, etc., 12
is the first memory section 11 and the first data bus 4c.
a first data sending control means capable of controlling the read data of the first memory section 11 not to be sent to the first data bus 4C by a control signal between the two; 13 is a first memory section; 11 and the first data transmission control means 12.

Reference numerals 21 to 25 are various parts within the memory monitoring circuit 2, and 21 is a second memory section composed of a semiconductor (IC) memory or the like;
22 is connected to the second memory section 21 by a control signal between the second memory section 21 and the second data bus 4f.
a second data sending control means 23 capable of controlling the read data of the memory circuit so as not to send it to the second data bus 4f; 1 is input via the second data bus 4f, and data read from the second memory section 21 is input via the internal bus 25, and both data are compared to make sure that both data are unified. A control signal is sent to the second data transmission control means 22 to prevent the read data from the second memory section 21 from being transmitted to the second data bus 4f when the data matches the second data bus 4f. An instruction signal for storing the address and data that caused the error is sent to the failure data storage means 24, and the data read from the second memory section 21 is sent to the second data bus 4f, and the data is stored in the first memory section. 24 is a data matching monitoring means for sending a control signal to the first and second data sending control means 12.22 to control not to send the read data of No. 11 to the first data bus 4c; When the instruction signal is received from the monitoring means 23, the address input from the processor 3 via the second address bus 4d and the address input from the first memory section 11 via the second data bus 4f are A failure data storage means 25 for storing read data is a second internal data bus for transferring data between the second memory section 21 and the second data transmission control means 22.

[For production]

In FIG. 1, a memory circuit 1 is a memory circuit that constitutes an electronic device, and a memory section 11 within the memory circuit 1 is, for example, a newly developed memory including built-in related circuits (not shown). On the other hand, the memory monitoring circuit 2 is a test memory circuit used to detect a failure in the memory section 11 when performing an operation test of an electronic device using the memory circuit 1. For the memory section 21 in 2, a memory with a proven track record of use is used.

The operation when detecting a failure in the memory section 11 of the memory circuit 1 will be described below. Note that the description of "first" or "first and second" will be omitted unless there is a risk of causing confusion.

The detection of a memory failure in FIG. 1 is not performed during a test of the memory function of the memory circuit 1, but rather detects any failure when the memory circuit 1 is used during an operation test of an electronic device. It is.

When the processor 3 writes data to the memory section 11 of the memory circuit 1 during the operation test, it specifies the address of the memory section 11 using the address bus 4a and the control bus 4b, performs write control, and writes the data to the data bus 4C. send and write the data. At this time, these information, control signals, and data are also sent to the memory section 21 of the memory monitoring circuit 2 via the common bus 4, and the memory sections 1.1.21 of the memory circuit 1 and the memory monitoring circuit 2 are The same data is written to the same address at the same time.

Next, when the processor 3 reads the data stored in the memory section 11 of the memory circuit 1, the address bus 4a
Data is read from the memory unit 11 via the control bus 4b, and the read data is sent to the processor 3 via the data bus 4c. At this time, the read data is transferred to the data bus 4c.
, the common bus 4 and the data bus 4f to the data coincidence monitoring means 23 of the memory monitoring circuit 2.

At this time, the same data is simultaneously read from the same address of the memory section 21 of the memory monitoring circuit 2 under the read control from the processor 3, but in a normal state, the data transmission control means 22 transfers the data read from the memory section 21 to the data bus. 4f, the data read from the memory section 21 is not sent to the common bus 4, and therefore the processor 3
The processor 3 receives only the data read from the memory section 11 of the processor 3, but the processor 3 does not read the data yet at this stage.

On the other hand, in the memory monitoring circuit 2, data read from the memory section 21 is inputted to the data coincidence monitoring means 23 through the internal data bus 25, and data read from the memory circuit 1 inputted through the data bus 4f is inputted to the data coincidence monitoring means 23 through the internal data bus 25. compared with the data obtained. If the comparison results match, the operation continues as is. However, if the two data do not match, the data matching monitoring means 23 sends a control signal to the data sending control means 12 of the memory circuit 1, and transfers the data from the memory section 11 to the data bus 4C. At the same time, the data transmission control means 2
A control signal is also sent to the memory section 21 to control the data read out from the memory section 21 to be sent to the data bus 4f. Therefore, data read from the memory section 21 in the memory monitoring circuit 2 is input to the processor 3 via the common bus 4. The processor 3 then reads the received data. That is, if the data read from the memory circuit 1 and the memory monitoring circuit 2 do not match,
The processor 3 uses the data read out from the memory monitoring circuit 2.

When the data coincidence monitoring means 23 of the memory monitoring circuit 2 detects a data mismatch, it sends an instruction signal to the failure data storage means 24 to store the address and data that caused the mismatch. The fault data storage means 24 stores the memory portion 11 of the memory circuit 1 sent through the data bus 4c.
The subsequent data and the address information sent to the address bus 4d are stored.

As described above, if the data in the memory circuit 1 and the memory monitoring circuit 2 do not match, the operation test is continued using the data read out from the memory section 21, which has a proven track record, so that efficient testing can be performed. Furthermore, memory failures can be analyzed at a later time by reading the failure data storage means 24. Furthermore, since memory failures can be detected through operational tests, testing of only memory functions can be kept to a minimum, greatly improving testing efficiency.

〔Example〕

FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a time chart of the embodiment of the present invention, and FIG. 4 is a block diagram of an electronic device according to an application example of the present invention.

5 The same symbols are used for the same objects throughout the figures, and 1
4 is a write/read controller for memory circuit 1, 26
is the write/read controller of memory monitoring circuit 2, 2
7 is a control signal line, 31 is a microprocessor, 32 is a memory package, 33 is an expansion package space, 34 is a maintenance console control package, 35 is a maintenance console, 36 is a communication path switch, and 37 is a communication path switch. The control device 38 is a common bus. Note that the bus driver/receiver 12 and write/read controller 14 of the memory circuit 1 and the bus driver/receiver 22 and write/read controller 26 of the memory monitoring circuit 2 play the roles of the data sending control means 12 and 22 in FIG. 1, respectively. It includes. 2 to 0 are points whose potential levels are illustrated in FIG. 3.

FIG. 4 shows a configuration diagram of a small capacity PBX (private branch exchange) as an example of an electronic device to which the present invention is applied. When the present invention is applied, the memory package 32 is a memory circuit 1 equipped with a newly developed semiconductor memory.
(Fig. 1, Fig. 2) corresponds to 6. Further, the expansion package space 33 is provided in advance for mounting a memory package etc. in the future, but when the present invention is applied, the memory monitoring circuit 2 shown in FIGS. 1 and 2 is mounted in this space. and perform an operation test.

First, the case where the processor 3 writes data to the memory section 11 of the memory circuit 1 during the operation test of the electronic device in FIG. 2 will be explained using FIG. 3 (1).
) As is clearer, memory circuit 1 and memory monitoring circuit 2
Memory circuit 1
Only the write operation to the memory unit 11 will be explained.

When the processor 3 writes data to the memory section 11 of the memory circuit 1, it sends address information to the address bus 4a as shown in (1) in FIG. 3(1). Then processor 3
sends a control signal for writing to the control bus 4b, which is decoded by the write/read controller 14 and sent to the bus driver/receiver 1.
2 and the memory section 11.

Among the write control signals, C3 at L level is first applied to a memory chip (not shown) to be selected in the memory unit 11.
1 (chip select) signal is sent to select a memory chip ((1)-■ in FIG. 3). Next, the gate of the bus driver/receiver 12 is opened by the C1 (gate) signal at the L level, and the RD1 (read) signal and the RWI (read/write 1-selection) signal are set at the L level and the memory unit 1 is opened.
1 to write state (Fig. 3 (1)-■
■■).

In the above state, as shown in (1) in Figure 3 (data bus 4
Data is sent to c and written into the memory section 11 by WPI (write pulse) ((1)-■ in FIG. 3). Note that, in parallel with the above, the same data is written to exactly the same address in the memory section 21 of the memory monitoring circuit 2.

Next, the third section describes the operation when the processor 3 reads data stored in the memory section 11 of the memory circuit 1 and successive data from each memory section IL21 of the memory circuit 1 and memory monitoring circuit 2 match. This will be explained with reference to FIG. (2).

The processor 3 connects to an address bus 4a via a common bus 4,
Address information is sent to 4d (Fig. 3 (2) ■■).

Next, L level C3I and CS2 signals are sent to the memory chips (not shown) to be selected in the memory section 11 and the memory section 21 via the control lot 4b, 4e and the write/read controller 14.24. Select the chip (Fig. 3 (2) ■@). Then RDI, R
The D2 signal and the RWIRW2 (read/write selection) signal are set to the I] level to set the read state, and the memory section LL
21 (Figure 3 (2) - ■■■
■).

In the above state, as shown in Figure 3 (2), the memory section I
Reading of data is started from L21, and the data read from the memory section 11 opens the gate of the hash driver/receiver 12 by the L level G1 signal, and is transferred to the internal data bus 13. Bus driver/receiver 12. The data is sent to the processor 3 through the data bus 4c and the common bus 4, but at the same time, it is input from the common bus 4 to the data coincidence monitoring circuit 23 in the memory monitoring circuit 2 via the data bus 4f. Further, the data read from the memory section 21 of the memory 9 monitoring circuit 2 is also input to the data coincidence monitoring circuit 23 through the internal data bus 25, and is compared with the successive data of the memory section 11. In this state, as shown in [phase] in FIG. 3 (2), the write/read controller I/roller 26 sends an H level to the G2 line, and the bus driver/receiver 2
Since the second gate is closed, the data read from the memory section 21 is not sent to the data bus 4f (the third gate is closed).
Figure (2) -@).

The data matching monitoring circuit 23 compares successive data in the memory section 11 and the memory section 21 using an internal strobe [phase].
If both data match, the process continues as is, and at time T, the data sent to the data bus 4c is read by the processor 3.

FIG. 3(3) is a time chart when the read data of the memory section 11 and the memory section 21 do not match in the above, and this will be explained below.

When it is determined that the data do not match when the internal strobe ■ is input to the data policy monitoring circuit 23, the data match monitoring circuit 23 sends control information to the write/read controller 26 to perform control when a mismatch is detected. Output. The light that received the control signal/
The read controller 26 outputs a pulse to the fault data storage circuit 24 via the WF2 line.
), the fault data storage circuit 24 stores the address information sent to the address bus 4d and the successive data of the memory circuit 1 sent to the data bus 4f, and also stores error information including the address information and data. (Figure 3 (3) -@).

Furthermore, at the time when the storage of the error information is finished, the write/read controller 26 sends control information to the write/read controller 14 of the memory circuit 1 via the error information line 27, and from the write/read controller 14 The 01 line, which was sending I level to the bus driver/receiver 12, is changed to H level. As a result, the gate of the bus driver/receiver 12 is closed, and the read data from the memory section 11 is no longer sent to the data bus 4c ((2)-■■ in FIG. 3).

Further, the write/read controller 10-26 of the memory monitoring circuit 2 changes the potential of the G2 line for the path driver/receiver 22 from the H level to the L level.
/In order to open the gate of the receiver 22, the data read from the memory section 21 is sent to the processor 3 via the data bus 4f.
(Fig. 3 (2)-@)■), and the test continues.

As described above, in the present invention, when a mismatch is detected, it is determined that the cause is in the memory section 11 whose evaluation is insufficient, and data from the memory section 21 that has a sufficient track record of use is used. Continue the operation test. Therefore, the operation test is not interrupted every time a memory failure occurs (the efficiency of the test is improved).

Furthermore, since the fault details are stored in the fault data storage circuit 24, they can be read out from the fault data storage circuit 24 later.
Since it can be analyzed all at once, troubleshooting can be done efficiently.

In addition, for the third product, for convenience of explanation, the signal level is changed at the necessary time, but some signals, for example C1,
The 02 line etc. may be set to the normal I] level, and set to the L level only when the game) is opened, and the RDI in the readout cycle will remain at the H level if the previous cycle is also a readout cycle, etc. There may be some differences from Fig. 3.

These do not pose problems in implementing the present invention.

Hereinafter, the present invention has been explained in detail with reference to FIGS. 2 and 3. However, FIGS. 2 and 3 are merely examples of the present invention, and there are many examples in which the configuration and operation are different from these. is assumed. For example, it is clear that the present invention is applicable even if a method of transmitting chip select information via an address bus is used, or by changing the transmission route of the control signal from the data coincidence monitoring circuit 23 when there is a mismatch. The present invention does not exclude these variations.

〔Effect of the invention〕

As explained above, according to the present invention, when a newly developed memory for which performance evaluation has not been sufficiently evaluated is employed in an electronic device, memory failure can be detected during the operation test 3 4 of the electronic device. As a result, testing of only memory functions can be kept to a minimum, and there is no need to interrupt testing every time a memory failure occurs, which greatly contributes to improving the testing efficiency of such electronic devices.

12, 22 1.3.25 3 4 It is.

Data transmission control means internal data bus Data matching monitoring means Fault data storage means

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a configuration diagram of an embodiment of the invention, Fig. 3 is a time chart of an embodiment of the invention, and Fig. 4 is a diagram illustrating the principle of the present invention.
The figure is a block diagram of an electronic device to which the present invention is applied, and FIG. 5 is a block diagram of a conventional technique. In the figure, 4a, 46 b 4e 4c, 4f 11 21 Memory circuit Memory monitoring circuit Processor common lot address lot control path data bus memory section

Claims (1)

Claims: comprising a first memory section (11) and a second memory section (21) connected to a processor (3) via a common bus (4), during a read cycle of said processor. data matching monitoring means (23) for collating data respectively read from the first memory section and the second memory section; writing the same data to the memory sections at the same time, and outputting only the read data from the second memory section to the common bus when a mismatch is detected by the data coincidence monitoring means in a read cycle of the processor; A memory fault detection method characterized in that the mismatched data and address are stored in a temporary storage circuit (24).