JPH0612277A - Method for inspecting information processing system - Google Patents

Abstract

PURPOSE:To inspect a logic circuit, which is operated only in the state of connecting another system controller, without connecting the other system controller by forming a return passage for returning an access request and response data to be transferred to the other system controller to the own system controller. CONSTITUTION:An address path 17 and a data path 18 connecting the two system controllers are returned and connected in the state of connecting only a first system controller 5. The access request is passed through a request priority circuit 11, main memory selection circuit 12 and address path 17, returned by a main memory comparator circuit 16 in the own device 5 and inputted to a main storage device 7. The data read from the main storage device 7 in respect to this access request are passed through the data path 18, returned at the data transfer port of the second system controller and transferred through a data transfer destination selection circuit 15 to an instruction processor generating the access request.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting an information processing system capable of connecting two system control devices in a pair, and more specifically to a logic which operates only when two system control devices are connected. The present invention relates to a method for inspecting an information processing system capable of inspecting a circuit or the like without connecting two system control devices.

[0002]

2. Description of the Related Art Generally, in an information processing system,
Even if the design allows two system controllers to be connected,
It is often shipped in a small-scale configuration with only one system controller. Then, in the future, the system may be expanded by additionally connecting the system control device.

Here, the system control device is an access request from the processor to an accessed device such as a main memory connected to the self device or to an accessed device connected to the other system control device. If it is for the accessed device connected to the own device, the access request is directly transferred to the accessed device connected to the own device, and the accessed device connected to the other system control device is accessed. If it is for a device, the access request is transferred to the corresponding accessed device via the other system control device, and the response data for the access request is sent to the processor of the access request source through the route corresponding to the transfer route of the access request. Is configured to reply to.

In such an information processing system,
When shipping in a small-scale configuration with only one system control unit, when there is a possibility that a new system control unit will be connected when the system is expanded in the future, the failure of the unique logic circuit etc. that operates for the first time when the system is expanded. In order to prevent problems caused by the above, it is necessary to inspect the relevant logic circuit and the like before shipping.

Therefore, in the past, a system controller dedicated to the inspection was prepared, and this was actually connected to perform the required inspection.

[0006]

However, when one system controller dedicated to the inspection is prepared and the inspection is performed by connecting the system controller, the cost of maintaining the system controller dedicated to the inspection and the connection / disconnection are performed. There is a problem that the number of steps is large and the inspection efficiency is extremely poor.

An object of the present invention is to provide an inspection method of an information processing system which can efficiently inspect a portion operating in a system extended state without preparing a system controller dedicated to the inspection.

[0008]

In order to achieve the above object, the present invention relates to an access request from a processor to an accessed device connected to its own device or to an accessed device connected to the other system control device. If it is for the accessed device connected to its own device, the access request is directly transferred to the accessed device connected to its own device, and the access request is sent to the other system control device. If it is for the connected accessed device, the access request is transferred to the corresponding accessed device via the other system control device, and the response data to the access request is sent through the route corresponding to the access request transfer route. It is equipped with a pair of system controllers that return to the processor of the access request source, and the other of the pair of system controllers is necessary. A method for inspecting information processing systems that are connected together, wherein the other of the pair of system control devices is not connected, and the access request signal output port of one system control device to the other system control device is Connected to the access request signal input port from the other system control device, the response data output port to the other system control device is connected to the response data input port from the other system control device, and the access request is sent to the other system control device. Set the criteria for determining whether or not to transfer to the system control unit to the same content as the state where a pair of system control units are connected, and access to one system control unit connected to the other system control unit By giving an access request to the device, it is possible to detect a logic circuit, etc. that operates only when the other system control device is connected. It was to perform.

[0009]

According to the above means, the access request signal output port of one system control device to the other system control device is connected to the access request signal input port of the other system control device, and the other system control device is controlled. The response data output port to the device is connected to the response data input port from the other system control device. That is, a connection path is formed by connecting a cable so that the access request and response data to be transferred to the other system control device are returned to and input to the own system control device. Furthermore, the criterion for determining whether or not to transfer the access request to the other system control device is set to the same content as the state in which the pair of system control devices are connected. In this state, an access request is issued to one system control device for the accessed device connected to the other system control device.

Then, the access request and response data to be transferred to the other system control unit are returned to the own system control unit by the return route of the cable.

As a result, the access request and response data pass through a logic circuit or the like that operates only when the other system control device is connected, so these logic circuits and the like should be connected to the other system control device. Can be inspected without.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to illustrated embodiments.

FIG. 1 is a block diagram showing an embodiment of the overall configuration of an information processing system to which the present invention is applied, showing a state in which two system control devices are connected in pairs.
In FIG. 1, 1-4 are first to fourth instruction processors (IP0-3), 5 is a system controller (SC0), 6
Is another system controller (SC1) connected to the system controller 5 in a pair, and 7 is the system controller 5
Is connected to the first main memory device (MS0), 8 is connected to the system control device 6 is the second main memory device (MS1)
Is.

The system control devices 5 and 6 here are
The main storage devices 7 and 8 are each composed of the same logic circuit.

In this structure, the instruction processors 1, 2, 3 and 4 generate memory access requests for independently accessing the main storage devices 7 and 8 via the system control devices 5 and 6 connected to the two pairs. Configure the device.

FIG. 2 shows instruction processors 1, 2, and 3, 4
Of the data transfer path of the system control devices 5 and 6 for the operation until the data read from the main storage device 7 or 8 is transferred to the instruction processor of the request source by a memory access request from It is an explanatory view for explaining with.

In FIG. 2, 11 and 21 are request priority circuits, 12 and 22 are main memory selection circuits, and 1
3, 23 are main memory access parameters, 14 is a transfer data selection circuit, 15 is a data transfer destination selection circuit, 16, 26
Is a main memory address comparison circuit, 17 is an address path between system controllers, and 18 is a data path between system controllers.

Memory access requests from the instruction processors 1 and 2 having the memory access right are fetched in the system controller 5. In the system controller 5, when one memory access request is selected by the request selection circuit 11, the address of the memory access request is sent to the main memory selection circuit 12 and the main memory access parameter 13.

In the main memory access parameter 13, selection information of the main memory devices 7 and 8 corresponding to each address (that is, information indicating which of the two main memory devices 7 and 8 should be selected) and its selection information. When the address in the main memory is stored and the address of the memory access request is input, the selection information of the main memory corresponding to the input address and the address in the main memory are read, and the selection information Is input to the main memory selection circuit 12 as a selection control signal.

The main memory selection circuit 12 selects one of the main memory devices 7 and 8 according to the selection information given from the main memory access parameter 13 and assigns the address of the memory access request to the main memory device. It is converted to the address in and transferred.

The main storage device 7 or 8 to which the address of the memory access request has been transferred reads a predetermined amount of data from the storage portion of the corresponding address and transfers it to the transfer data selection circuit 14.

The transfer data selection circuit 14 selects the same data path on the main memory device side as the main memory device 7 or 8 selected by the main memory selection circuit 12, and transfers the data to the data transfer destination selection circuit 15. To do. The data transfer destination selection circuit 15 selects a path to the same instruction processor as the instruction processor selected by the request selection circuit 11 and transfers the requested data.

This operation is similarly performed in the system controller 6 even when an access request is output from the second and third instruction processors 3 and 4.

When the first main memory device 7 is selected by the main memory selection circuit 12, the address of the memory access request is directly transferred to the first main memory device 7, but the second main memory device 7 is selected. When the memory device 8 is selected, the address of the memory access request may be directly transferred to the second main memory device 8 or may be temporarily transferred to the second system control device 6. In either case, the same operation is performed for the present invention, but FIG. 2 shows an example in which the operation is once transferred to the second system control device 6. In addition, the main memory access parameter 13 can normally change the in-memory arrangement when there is a failure in the main memory 7 or 8 or when the mounting capacity of the main memory 7 or 8 is irregular. The parameters are rewritable.

That is, assuming that the access request address for the main storage devices 7 and 8 is "0 to 200",
When the two main storage devices 7 and 8 are connected in a normal state, the access request address “0 to 100” is “0 to 100” in one main storage device 7, as shown in FIG.
Is output and selection information (MS0) for selecting the main memory 7 is output, and the access request address "101-200" accesses "0-100" of the other main memory 7. The parameters are set so that the selection information (MS1) for selecting the main storage device 8 is output.

However, when the other main memory 8 fails, the access request addresses "0-100" and "101-200" are "0" in the normal main memory 7, as shown in FIG. 3B. .About.200 "is accessed, and the parameters are changed so that only the selection information (MS0) for selecting the main storage device 7 is output.

FIG. 4 shows the configuration and signals in the case where the cable between the system control devices is folded back and connected in order to inspect the operation of the first system control device 5 in the state where the second system control device 6 is not connected. It is a block diagram showing the flow of data.

In FIG. 4, each circuit in the first system control device is the same as that in FIG. 2, but an address path 17 and a data path 18 connecting between the system control devices 5 and 6 are connected back to each other, An address conversion circuit 31 is provided at the output port of the address path 17.

In this configuration, the process of accessing the main memory device 7 in response to a memory access request from the instruction processor 1 or 2 having the memory access right is shown in FIG.
It is as explained in.

Normally, in a system composed of only one system controller, the main memory access parameter 13
Is set to always access the main storage device connected to the own system control device in response to a memory access request of any address.

That is, for example, in the first system controller 5, as shown in FIG. 3B, parameters are set so that only the main storage device 7 connected to the own device 5 is accessed. There is.

Therefore, in the configuration in which only the first system control device 6 is connected, the address path 17 and the data path 18 connecting the system control devices 5 and 6 are connected back to each other and the main memory access is performed. The parameters are rewritten so as to access the main storage device 8 connected to the partner system control device 6. That is, the parameters are changed to those shown in FIG. Then, the instruction processor 1 or 2 outputs an access request for accessing the main storage device 8.

Then, this access request is returned to the main memory comparison circuit 16 in the own device 5 via the request priority circuit 11, the main memory selection circuit 12, the address conversion circuit 31, and the address path 17, and this main memory comparison circuit 1
It is input to the main storage device 7 via 6.

The data read from the main storage device 7 in response to the access request is sent to the data transfer port of the system control device 5 to the second system control device 6, but the data is transferred to the second system control device 6 via the data path 18. 2 system controller 6
Instruction processor 1 which has returned to the data transfer port from the device, is guided again to the transfer data selection circuit 14 of its own device 5, and has issued the access request via the data transfer destination selection circuit 15.
Or transferred to 2.

By such an operation, in the configuration in which only one system control device 5 is connected, it is possible to perform the same inspection as in the state in which the two system control devices 5 and 6 are connected.

By the way, in general, the two system control devices 5 and 6 may prohibit the simultaneous execution of main memory access to the same address. In such cases,
Even if the inspection is performed by the above method, it may not operate properly due to address conflict between the system control devices.

As a method of prohibiting the simultaneous execution of main memory access to the same address between the two system control devices 5 and 6, the main memory address coming from another system control device is set to the main memory in its own system control device. There is a method of comparing with the address and stopping one of them if they match.

In the example of FIG. 2, when the same address comes from the inter-system controller address path 17 at a timing later than the address output from the main memory selection circuit 22, the main memory address comparison circuit 26 causes the first system to operate. The main memory access in the control device 5 is held for a certain time.

However, in the example of FIG. 2, if the main memory device to be accessed is different, it is not necessary to compare this address, so the main memory address comparison circuit 16 in the example of FIG.
Will never work. However, an actual information processing system has a cache memory in the instruction processor and the system control unit, and if only part of the address matches due to the control of this cache memory, access to the main memory is not allowed. Since it may be temporarily suspended, the main memory address comparison circuit 16 of FIG. 4 may operate.

In this case, if the address returned by the inter-system controller address path 17 of FIG. 4 is different from the original memory access request address, no address conflict occurs and the operation is performed without any problem.

Therefore, when the access request address is transmitted through the inter-system controller address path 17, if the address is converted by the address conversion circuit 31, address conflict does not occur and the operation can be performed without any problem.

For this conversion method, an appropriate conversion method is selected according to the structure of the system to which it is applied.

As described above, according to this embodiment, in a system in which two system control devices 5 and 6 can be connected, even when only one system control device is connected,
It is possible to inspect a logic circuit or the like that operates only when two system control devices are connected without causing an address conflict.

Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Nor. For example, although the access target is the main storage device, the present invention can be similarly applied to an accessed device such as another data input / output device that is accessed by the processor.

[0045]

As described above, according to the present invention,
With the other of the pair of system control units unconnected, connect the access request signal output port of one system control unit to the other system control unit to the access request signal input port of the other system control unit. , The response data output port to the other system control device is connected to the response data input port from the other system control device, and a pair of criteria for determining whether or not to transfer the access request to the other system control device is set. By setting the same contents as the state in which the system control unit is connected and by giving one system control unit an access request for the accessed device connected to the other system control unit, the other system control unit Since it is designed to test the logic circuit that operates only in the connected state, a system controller dedicated to the test is required. Without meaning, can a portion operating in a system extension state efficiently inspected,
It is extremely useful in practice.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of an information processing system to which the present invention is applied.

FIG. 2 is a block diagram showing a detailed configuration inside a system control device in FIG.

FIG. 3 is an explanatory diagram showing an example of contents of a main memory access parameter.

FIG. 4 is an explanatory diagram of a method of inspecting a portion that operates when two system control devices are connected by only one system control device.

[Explanation of symbols]

1 ... 1st instruction processor, 2 ... 2nd instruction processor, 3 ... 3rd instruction processor, 4 ... 4th instruction processor, 5 ... 1st system control device, 6 ... 2nd system control device, 7 ... 1st main memory, 8 ... 2nd main memory, 11 ... Request priority circuit, 12 ... Main memory selection circuit, 13 ... Main memory access parameter, 14
... transfer data selection circuit, 15 ... data transfer destination selection circuit,
16 ... Main memory address comparison circuit, 17 ... System controller address path, 18 ... System controller data path, 21 ... Request priority circuit, 22 ... Main memory selection circuit, 23 ... Main memory access parameter, 26 ...
Main memory address comparison circuit, 31 ... Address conversion circuit.

Claims (2)

[Claims] 1. A processor determines whether an access request from a processor is to an accessed device connected to its own device or to an accessed device connected to the other system control device, and is connected to its own device. If the access request is for an accessed device that is connected to its own device, the access request is directly transferred to the accessed device that is connected to its own device. A pair of system control devices for transferring the response data to the corresponding accessed device via the other system control device and returning the response data to the access request to the processor of the access request source through the route corresponding to the transfer route of the access request. , The other of the pair of system control devices is an inspection method of an information processing system connected as necessary. , The access request signal output port of one system control device to the other system control device was connected to the access request signal input port of the other system control device while the other of the pair of system control devices was not connected. In addition, the response data output port to the other system control device is connected to the response data input port from the other system control device, and a pair of criteria for determining whether or not the access request should be transferred to the other system control device is set. Other system control device by setting the same contents as the connected state of the other system control device and by giving one system control device an access request to the accessed device connected to the other system control device. Of an information processing system characterized by inspecting a logic circuit or the like that operates only in a state in which a computer is connected . 2. The system control device having means for prohibiting simultaneous access to the same part of the accessed device changes and outputs the content of the access request transferred to the other system control device. An inspection method for an information processing system according to claim 1.