JPH067379B2 - Direct memory access control circuit - Google Patents

Description

The present invention relates to a direct memory access control circuit used in a computer system to which a direct memory access device is connected.

"Prior Art" When performing data transfer processing from an input / output device to another memory device, there is a type in which a function of performing a data transfer processing operation is added to the input / output device in order to improve the efficiency. This is a direct memory access (hereinafter DMA
It is called a device. FIG. 7 shows an example of a computer system to which such a DMA device is connected.

This system includes a first bus 11 ₁ directly connected to a microprocessor (hereinafter referred to as CPU) 10 and a C
It has a _second bus 11 ₂ indirectly connected to the PU 10, and the first bus 11 ₁ and the second bus 11 ₂ are connected by a bus control circuit 12.

For example, one memory device 14 ₁ (this is called a first memory device) is connected to the first bus 11 ₁ . In addition, one DMA device 13 and one DMA device 1 are provided on the second bus 11 _2.
One memory device 14 ₂ (this is called a second memory device) is connected.

The DMA device 13 uses the first memory device 14 as necessary.
Data transfer processing is mutually performed with the _first or second memory device 14 ₂ . The bus control circuit 12 is a DMA
It is provided to control the transfer of the DMA request (DMA request) of the device 13 and various signals for execution thereof between the first bus 11 ₁ and the second bus 11 ₂ .

FIG. 8 is a block diagram of the bus line configuration and the bus control circuit 12.

(Structure of Bus Line) In the figure, the first part is provided on the left side of the bus control circuit 12.
The bus 11 ₁ connected, ₂ second bus 11 is connected to the right side of the bus control circuit 12.

The first bus 11 ₁ is composed of nine kinds of transmission lines each composed of one or a plurality of parallel transmission lines as shown in the figure, and the second bus 11 ₂ is also composed of eight kinds of transmission lines. It is configured.

Each transmission line is called by a name corresponding to these functions, and DMA
DMA request for transmitting request signal 11 ₁₁ , 11 ₂₁ ,
DMA request OK for transmitting a signal that permits DMA
11 ₁₂ , 11 ₂₂ , address buses 11 ₁₃ , 11 ₂₃ for transmitting address signals, bus active 11 ₁₄ , 11 ₂₄ for transmitting a signal indicating whether or not a bus line is in use, from the DMA device 13 shown in FIG. read / write mode 11 ₁₅ for transmitting a write signal for writing the read signal or the memory device 14 ₁ in the opposite, 14 ₂ of the contents when the data is to be written into the memory device 14 ₁ or 14 ₂ to the DMA device 13, 11 ₂₅ , strobes 11 ₁₆ and 11 ₂₆ for transmitting strobe signals for controlling the data writing operation, reply 1 for transmitting a response signal indicating that the data writing has been completed
1 ₁₇ , 11 ₂₇ , data buses 11 ₁₈ for transmitting data, 1
1 ₂₈ , and a restart 11 ₁₉ for transmitting a timing pulse for restarting the operation of the CPU 10 shown in FIG.

Here, hereinafter, the term "first" is attached to the transmission path belonging to the first bus 11 _1, and the term "second" is attached to the transmission path belonging to the second bus 11 _2. To do.

(Configuration of Bus Control Circuit) On the other hand, the bus control circuit 12 includes a DMA request / OK control 21, an address bus transceiver 2
2, address decoder 23, CPU restart timing generator 26, timing gate control 2
4 and a data bus transceiver 25.

The DMA request / OK control 21 uses the second D
A circuit having gates connected to each other so as to transfer the signal of the MA request 11 ₂₁ to the first DMA request 11 ₁₁ and transfer the signal of the first DMA request OK 11 ₁₂ to the second DMA request OK 11 ₂₂ is there.

The address bus transceiver 22 and the data bus transceiver 25 are circuits each having a bidirectional gate that transfers an address and data in a designated direction.

Address decoder 23, a second address transmitted through the second bus 11 ₂₃ which is connected to the first memory device 14 ₁ thing or the second bus 11 ₂ connected to the first bus 11 ₁
It is a circuit for determining whether or not the memory device 14 ₂ is for outputting a signal 27 for identifying it.

The dimming gate control 24 outputs the transfer direction designation signal 28 described above to the address bus transceiver 22 and the data bus transceiver 25 based on the identification signal 27 of the address decoder 23.

Further, the timing gate control 24 is provided between the read / write modes 11 ₁₅ and 11 _{25 of} the first bus 11 ₁ and the second bus 11 ₂ and between the strobes 11 ₁₆ and 11 ₂₆ .
It is a circuit having a gate that bidirectionally connects between the replies 11 ₁₇ and 11 ₂₇ and a gate that connects the first bus active 11 ₁₄ and the second bus active 11 ₂₄ as needed.

The CPU restart timing generator 26 has a second
Is a circuit which monitors the bus active 11 ₂₄ and outputs the restart signal of the CPU to the restart 11 ₁₉ at the timing of its fall.

(Operation of Bus Control Circuit) The operation of the circuit of FIG. 8 will be described with reference to the timing chart of FIG. 9 while comparing FIG. 7 to FIG.

First, DMA unit 13 shown in FIG. 7 is a second bus 11 ₂
A case will be described in which data transfer processing is performed with the _second memory device 14 ₂ connected to. DMA device 13 to DM
When the A request signal is issued, the second DMA request 11 ₂₁
Rises (FIG. 9 (a)), this signal is directly transferred to the first DMA request 11 ₁₁ through the DMA request / OK control 21.

In response to this, the CPU 10 receives the first DMA request O
K11 ₁₂ is raised ((b) in the same figure). And at the same time,
The use of the first bus 11 ₁ which has been used up to now is stopped and the first bus active 11 _{14 is made} to fall ((c) in the same figure).

When the second DMA request OK11 ₂₂ is falls, DMA
The device 13 drops the second DMA request 11 ₂₁ ,
The second bus active 11 ₂₄ is started up ((d) in the same figure). Then, the mode designating signal is placed in the second read / write mode 11 ₂₅ , and the address signal and the data are sent to the second address bus 11 ₂₃ and the second data bus 1 respectively.
Put on ₂₈ .

Thereafter, the DMA device 13 outputs a strobe pulse to the second strobe 11 ₂₆ every time one word of data is output to the second data bus 11 ₂₈ ((h) in the figure). Then, the second memory device 14 ₂ outputs a response signal to the second reply 11 ₂₇ each time.

When the series of data transfer processing is completed, the DMA device 13 causes the second bus active 11 ₂₄ to fall.
((D) of the same figure). The CPU restart timing generator 26 detects this and outputs a restart pulse to the restart 11 ₁₉ .

Upon receiving the restart pulse, the CPU 10 raises the first bus active 11 ₁₄ and restarts the operation.

FIG. 10 is a timing chart when the DMA device 13 shown in FIG. 7 performs a data transfer process with the first memory device 14 ₁ connected to the first bus 11 ₁ .

This content is almost the same as in FIG. 9, but the response signal is
That output to the reply 11 ₁₇ first memory device 14
_The difference is that it is 1.

Then, during operation of the data transfer processing shown in FIG. 9, the first bus 11 ₁ is not used at all, during the operation of the data transfer processing shown in FIG. 10 ₁ and the first bus 11 The difference is that both _second buses 11 ₂ are used.

[Problems to be Solved by the Invention] As described above, in the computer system shown in FIG. 7 having the bus control circuit 12 shown in FIG. 8, the DMA device 13 performs the data transfer process. During that time, the operation was unconditionally stopped.

However, when the DMA device 13 performs a data transfer process with the second memory device 14 ₂ connected to the second bus 11 ₂ , the first bus 11 ₁ directly connected to the CPU 10 is completely not being used.

Various devices (not shown) are connected to the first bus 11 _{1, and} it is not preferable to stop the CPU 10 during this period in terms of execution efficiency.

The present invention has been made in view of the above points, and an object of the present invention is to provide a direct memory access control circuit that improves the execution efficiency of a CPU.

"Means for Solving Problems" A memory access control circuit of the present invention includes a first bus directly connected to a microprocessor, a second bus indirectly connected to the microprocessor, and A bus control circuit for connecting the first bus and the second bus, and the bus control circuit includes the second bus
The direct memory access device connected to the bus of the microprocessor makes a direct memory access request to the microprocessor, and the microprocessor stops the operation of the microprocessor for the first bus on condition that the microprocessor acknowledges the request. The direct memory
When the access device specifies the address of the memory connected to the second bus at the start of the data transfer process, at this stage before the data transfer process by the direct memory access device is completed, the microprocessor sets the first It is characterized by permitting the operation using the bus. "Operation" As described above, in the direct memory access control circuit of the present invention, the second bus indirectly connected to the microprocessor is connected to the DMA device and the second bus. While being used by the memory device, the first bus directly connected to the microprocessor is used in parallel to increase the execution efficiency of the microprocessor.

The bus control circuit separates the first bus and the second bus so that they can be used independently.
This bus control circuit outputs an instruction signal for stopping or permitting the operation to the microprocessor.

When the DMA device makes a DMA request to the microprocessor, the microprocessor normally suspends its operation once, but at the start of the data transfer process, the DMA device is connected to the second bus. When the address of the memory device is designated, the bus control circuit detects this and restarts the operation of the microprocessor.

This makes it possible to improve the computer system, for example, simply by changing the configuration of the conventional bus control circuit.

[Embodiment] (Outline of bus control circuit and its operation) The direct memory access control circuit of the present invention is used in a computer system as shown in FIG. 7, and the bus control shown in FIG. The configuration of the circuit 12 is changed as shown in FIG.

In this figure, the configurations of the first bus 11 ₁ and the second bus 11 ₂ are the same as those described with reference to FIG. 8, and the same parts are designated by the same reference numerals and redundant description will be omitted.

Also, the blocks constituting the bus control circuit 32 are almost the same except for the wiring around the CPU restart timing generator 36, and the same portions are denoted by the same reference numerals and the duplicated description will be omitted.

In the bus control circuit 32 shown in FIG. 1, the CPU restart timing generator performs the following operation.

The conventional generator 26 shown in FIG. 8 captures the trailing edge of the second bus active 11 ₂₄ , generates a restart pulse at that timing, and sends it to the restart 11 ₁₉ .

CPU Li start timing generator 36 of the circuit of the present invention, on the other hand, as the first view, and receiving an output identifying signal 27 of the second bus active 11 ₂₄ and an address decoder 23. Then, this identification signal 27
From the first memory device 14 ₁ connected to the first bus 11 ₁ to the DMA device 13 shown in FIG. 7 or the second memory 11 ₂ connected to the second bus 11 ₂ . It is determined whether or not data transfer processing is to be performed with the memory device 14 ₂ of the second bus. In the former case, a restart pulse is output when the second bus active 11 ₂₄ falls, and in the latter case, the second bus active 11 ₂₄ is output. A restart pulse is output when the active signal 11 ₂₄ rises.

FIG. 2 is a timing chart for explaining the operation.

First, DMA request / OK control 21
Connects the second DMA request 11 ₂₁ to the first DMA request 11 ₁₁ and sends the first DMA request OK 1
1 ₁₂ is connected to the second DMA request OK11 ₂₂ .

When the DMA device 13 causes the second DMA request 11 ₂₁ to fall (FIG. 2 (a)), the CPU 10 responds to this.
Causes the first DMA request OK11 ₁₂ to rise (FIG. 11B), and the first bus active 11 ₁₄ to rise almost simultaneously (FIG. 11C).

On the other hand, the DMA device 13 causes the second bus active 11 ₂₄ to rise ((e) in the figure), the second address bus 11 ₂₃ , the second data bus 11 ₂₈ , and the second read / write. The data transfer process is started using the write mode 11 ₂₅ and the second strobe 11 ₂₆ ((f) to (i) in the figure). Then, the reply pulse is output from the second memory device 14 ₂ of the other party to which the DMA device 13 performs the data transfer processing to the second reply 11 ₂₇ ((j) in the same figure).

On the other hand, at this time, the address decoder 23 outputs an identification signal 27 indicating that the _second memory device 14 ₂ is used (solid line in FIG. 7D). This state is called a state in which the second memory space 27 has risen. That is, the second bus active 11 ₂₄ rises, and the address signal designating the address of the second memory device 14 ₂ is the second address bus 1
At 1 ₂₃ , the second memory space 27 rises.

At the timing when the second memory space 27 rises and the second bus active 11 ₂₄ rises, the restart pulse 53 is output to the restart 11 ₁₉ ((K) in the figure).
Solid line).

In response to this restart pulse 53, the CPU 10 makes the first
The bus active 11 ₁₄ is started up and the operation is started using the first bus 11 ₁ irrelevant to the operation of the DMA device 13 (solid line in FIG. 7C).

Conversely, when the DMA device 13 performs data transfer processing with the first memory device 14 ₁ , the second memory space 2
The signal 7 does not rise (broken line in FIG. 7D). At this time, the restart pulse 53 '(the pulse shown by the broken line in FIG. 2K) is output when the second bus active 11 ₂₄ falls.

Upon receiving the restart pulse, the CPU causes the first bus active 11 ₁₄ to rise (broken line (c) in the figure) and restarts the operation.

As described above, in this embodiment, the timing for generating the restart pulse to be sent to the CPU is set to either the rising edge or the falling edge of the second bus active 11 ₂₄ , thereby the operation Adjust the restart timing.

Incidentally, when the DMA device 13 shown in FIG. 7 performs the first memory device 14 ₁ and the data transfer process, in Figure 1, the timing gate control 24 and the first bus active 11 ₁₄ second bus Direct connection with active 11 ₂₄ . In the opposite case, all the transmission lines including the address buses 11 ₁₃ and 11 ₂₃ and the data buses 11 ₁₈ and 11 ₂₈ connected by the timing gate control 24 are disconnected. There are various possible circuits for generating such a restart pulse, one example of which will be described with reference to FIG.

(Explanation of CPU Restart Timing Generator) FIG. 3 is a block diagram of the CPU restart timing generator 36 suitable for being provided in the bus control circuit of the direct memory access control circuit of the present invention, and FIG. 4 shows its operation. 3 is a timing chart for explaining the above.

This generator has the second memory space 27 and the second bus active 11 ₂₄ connected to its input side and the restart 11 ₁₉ connected to its output side, as described above with reference to FIG. Has been done.

First, the signal of the second bus active 11 ₂₄ is input to both the rising edge detection circuit 41 and the falling edge detection circuit 42, the rising pulse 51 is output from the former at the timing of the rising edge, and the latter outputs the rising edge pulse 51 from the falling edge. Falling pulse 5 at the timing
2 is output.

The second bus active 11 ₂₄ , (c) is shown in FIG. 4 (b).
The rising pulse 51 is shown in FIG. 4 and the falling pulse 52 is shown in (d). The rising pulse 51 is supplied to the AND circuit 4 of FIG. 3 together with the second memory space 27 (FIG. 7A).
3 and the falling pulse 52 is input to the AND circuit 44 together with the inverted signal of the second memory space 27.

The outputs of the two AND circuits 43 and 44 are merged by the OR circuit 45 to form a restart signal.

Here, when the second memory space 27 is rising, the rising pulse 51 is output from the AND circuit 43 as it is, but the AND circuit 44 does not pass the falling pulse 52. Therefore, the restart pulse 53 shown by the solid line in FIG. 4 (e) is output from the generator 36 toward the restart 11 ₁₉ .

In this way, the restart pulse 52 can be output at the rising timing of the second bus active 11 ₂₄ .

On the other hand, when the second memory space 27 has not risen (broken line in FIG. 4A), the rising pulse 51 is not output from the AND circuit 43 and the falling pulse 52 is output from the AND circuit 44. . Since this is output toward the restart 11 ₁₉ , the restart pulse 53 'is output at the falling timing of the second bus active 11 ₂₄ as shown by the broken line in FIG. 4 (e).

FIG. 5 is a block diagram showing the rise detection circuit 41 and the fall detection circuit 42 of FIG. 3 in more detail. Also,
FIG. 6 is a timing chart for explaining the operation.

In this figure, the rising detection circuit 41 is composed of two flip-flops 41 ₁ and 41 ₂ , an AND circuit 41 ₃ and a delay line (DL) 41 ₄ . The fall detection circuit 42 is composed of an inverter 42 ₁ and an AND circuit 42 ₂ .

Now, each flip-flop 4 of the rising edge detection circuit 41
The clock signal 60 is supplied to 1 ₁ and 41 ₂ (FIG. 6 (b)), and the signal on the second bus active 11 ₂₄ is transferred from the flip-flop 41 ₁ in synchronization with the timing of this clock signal 60. The data is transferred to the AND circuit 41 ₃ through the flip-flop 41 ₂ ((c) and (d) in FIG.
(E), (f)).

A signal obtained by inverting the Q output of the flip-flop 41 ₂ is input to one terminal of the AND circuit 41 ₃ ((f) in the figure).

The second bus active is directly connected to the other terminal of the AND circuit 41 ₃ (((c) in the same figure). The AND outputs of both are input to the AND circuit 43 through the delay line 41 ₄ (see the same figure). (G)).

On the other hand, the fall detection circuit 42 uses the second bus active 1
The signal on 1 ₂₄ is inverted by the inverter 42 ₁ and input to one terminal of the AND circuit 42 ₂ , and the Q output of the flip-flop 41 ₂ of the rising edge detection circuit 41 is input to the other terminal (Fig. e)). This AND circuit 42 ₂
Is directly input to the AND circuit 44 ((h) in the figure).

Here, the delay line 41 ₄ is provided to match the timing because it takes some time for the second bus active 11 ₂₄ to rise and the second memory space 27 to rise.

In this way, the rising pulse 51 (FIG. 9 (g)) is obtained from the rising edge detection circuit 41, and the falling pulse 52 (FIG. 3 (h)) is obtained from the falling edge detection circuit 42.

After that, as described with reference to FIG. 3, when the second memory space 27 is rising, the second bus active 1
Restart pulse 53 at the timing 1 ₂₄ rises (sixth
The solid line in the figure (i) is output, and the second memory space 2
When 7 is not rising, the second bus active 11
_{At the} timing when ₂₄ falls, restart pulse 53 '(6th
The broken line in Fig. (I) is output.

"Effects of the Invention" The direct memory access of the present invention described above
The control circuit, in the second bus indirectly connected to the microprocessor, controls the microprocessor while performing data transfer processing between the DMA device and the second memory device connected to the second bus. Since the microprocessor can perform other processing by using the first bus directly connected to the processor, its execution efficiency can be improved.

Further, according to the present invention, the microprocessor side can control the second bus without being aware of the existence of the second bus. That is, whether the microprocessor has a direct memory access device connected to the first bus or a second bus.
Without distinguishing whether this is connected to the bus of
When there is a direct memory access request, the operation is stopped. Further, when the direct memory access device connected to the second bus designates the second bus and performs the data transfer process, the direct memory access device connected to the first bus is the first bus. When the data transfer process is performed on the first bus, the use of the first bus is permitted by obtaining from the bus control circuit a signal (restart pulse in the embodiment) that is simulated as the end of the process. . In this way, the microprocessor side does not need to be aware of the bus configuration,
Since the access request can be dealt with, there is no need to change the control program even if the system is changed, and the bus can be easily added or changed.

Further, in the case of the present invention, when a direct memory access request is issued, the microprocessor is notified of this request and the operation of the microprocessor is stopped as a result of the request being acknowledged by the microprocessor. In other words, the microprocessor is able to transfer data on the bus independently of the microprocessor.
Knows the request to start and has the right to decide whether to accept the request. Therefore, if some failure occurs and the microprocessor determines that it is not desirable to continue control, it may stop its progress even if it is a data transfer on the second bus. it can. On the other hand, in a system in which the first bus and the second bus are separated in a normal state, data processing on the second bus proceeds without the involvement of the microprocessor, which is inconvenient for the system. May occur.

Further, in the case of the present invention, regardless of which bus is used for data transfer, the microprocessor stops its operation, and the data transfer by the direct memory access device is performed on the bus that is not directly related. The operation is started when it is determined that the data is to be stored, or when the next determination situation occurs such that the direct memory access is completed on the directly connected bus. Therefore, even if some disturbance occurs at the start of data processing on another bus, the microprocessor is not affected by the disturbance, and the reliability can be ensured.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bus control circuit provided in the direct memory access control circuit of the present invention, and FIG. 2 is a timing for explaining the operation of the direct memory access control circuit of the present invention. The chart and FIG. 3 show the direct memory of the present invention.
A block diagram showing an embodiment of the main part of the access control circuit, FIG. 4 is a timing chart thereof, and FIG. 5 is a block showing a more detailed embodiment of the main part of the direct memory access control circuit of the present invention. Figure, 6th
FIG. 7 is a timing chart thereof, FIG. 7 is a block diagram of a computer system suitable for implementing the present invention, FIG. 8 is a block diagram showing an example of a conventional bus control circuit, and FIGS. 9 and 10 explain its operation. 7 is a timing chart for performing the operation. 10 ... Microprocessor, 11 ₁ ...... First bus, 11 ₂ ...... Second bus, 12 ...... Bus control circuit, 13 ...... Direct memory access device, 14 ₁ ...... First memory device , 14 ₂ ...... Second memory device.

Claims (1)

[Claims] 1. A first directly connected to a microprocessor.
Bus, a second bus indirectly connected to the microprocessor, and a bus control circuit that connects the first bus and the second bus, and the bus control circuit includes the second bus. Of the direct memory access device connected to the bus of the microprocessor makes a direct memory access request to the microprocessor, and stops the operation of the microprocessor for the first bus on condition that the microprocessor acknowledges the request. When the direct memory access device specifies the address of the memory connected to the second bus at the start of the data transfer process, this step before the data transfer process by the direct memory access device is completed And permitting the microprocessor to perform operations using the first bus. Memory access control circuit.