JPS63251840A - Control method for detection of multi-processor abnormality - Google Patents

Abstract

PURPOSE:To prevent the progress of a fault and to improve the reliability of a multi-processor system by keeping an abnormal cycle under a waiting state when the fault occurs in the system. CONSTITUTION:When a memory has a fault, a flip-flop 2 is set by a NAND 8 when the abnormal cycle is equal to the cycle of a CPU-2 via a fault generation signal 3C. Then an interruption request 1F is supplied by the output of the flip-flop 2 against a CPU-1. At the same time, the output of a counter 3 is inhibited by a NAND 7, therefore, a waiting state 2E of the CPU-2 is not released. Then the state 2E is released when a control signal received from the CPU-1 is reset. Thus the state 2E is not released and a processor is kept under the state 2E when a fault occurs. Thus it is possible to prevent the progress of an error state and to improve the reliability of a multi-processor system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a system for detecting and controlling failures occurring in a multiprocessor system having a shared memory, and
Place 1! The present invention relates to a method for detecting and controlling a failure occurring in a slave processor in a multiprocessor system consisting of an If device and a cousin III LQ device.

(Prior art) Conventionally, in a multiprocessor system with a collaborative memory system, an error was detected by reflecting the occurrence of a failure in the memory contents and having each processor read the contents using a semaphore. -254303), and in a multiprocessor system composed of a main processing unit and a slave processing unit, a response waiting timer is provided in the main processing unit and the occurrence of a failure is detected by monitoring the status of the slave processing unit. Recently, in order to shorten the failure detection time, a self-notification request command for the slave processing device has been set at the firmware level, and the judgment is made based on whether a response from the slave processing device can be obtained within a predetermined time. (Japanese Unexamined Patent Publication No. 00-254338).

(Four Points to be Solved by the Invention) Conventional techniques can instantly resolve failures that occur not only in multiprocessor systems with shared memory, but also in multiprocessor systems composed of a main processor KU and a slave processor LM. Undetectable. In other words, the processor continues to operate in an abnormal state after a failure occurs until some method is taken to deal with the failure, resulting in a worsening of the situation. In the worst case, the system may go down before the failure is detected.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a highly reliable multiprocessor control method that eliminates the above-mentioned drawbacks and prevents the error state from progressing in the event of a failure.

[Means for solving problems]

The present invention provides a multiprocessor in which at least two or more CPUs have a shared memory, and when at least one of the processors accesses the shared memory, a wait is applied to the CPU to check for errors in the coexisting memory. If the memory abnormality detection circuit detects an error, it is characterized in that 11 of the wait messages are sent in succession.

(Operation) In this method, the cycle of the processor and the processor is used as a wait table at the time of occurrence of a failure.Therefore, each processor of the multiprocessor system having a shared memory, and the multiprocessor system consisting of the main processing unit and the slave processing unit, First, a wait is placed on the processor in each processing unit of the processor system at the start of a cycle.If no failure occurs, the wait is immediately released, so no unnecessary wait is inserted.When a failure occurs, the wait is canceled. The processor or processing device remains in a wait state and does not move on to the next process.Furthermore, the occurrence of a failure is detected by sending a signal from the interrupt generation circuit to another processor or other processing device using a hardware signal. This is done by interrupt.

〔Example〕

The present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a system configuration for implementing the present invention in a multiprocessor system that uses common memory.
In the figure, 1 is the main processor, CPU-1,
2 is a sub-processor CPU-2. An access request to the co-located memory 5 of each processor is CP of 1.
U-1 is ID12 and CPU-2 is 20, and after arbitration by the competition circuit 4, the permission signal for ID becomes IG, and the permission signal for 2C becomes 2D, which are respectively output exclusively. Based on the 1G and 2D memory access permission signals, the memory access control circuit 7 generates a control signal 3D for the memory. This 3D signal, address 3A, data 31
3, the coexistence memory 5 performs data output. Also, in synchronization with this timing, the memory foreign detection circuit 6 determines whether access to the shared memory 5 is normal. If an abnormality is detected, an abnormality occurrence detection signal 3C is output. Normally, abnormality detection is performed by a parity check or a CRC check.

A timing chart when CPU 1 and CPU 20 access the coexisting memory 5 is shown in FIG. 1's CI) The access request ID for the coexisting memory 5 from U-1 is output, and the contention avoidance circuit 4 arbitrates the access request ID, and the access permission signal IG for the 1's CPU-1 is output. At that time, the access request 2c to the shared memory 5 from CPU-2 of 2 is contention Ll until the request of LD is released.
il Since it is not permitted by trace circuit 4, it will remain in the same state. On the cPU-1 side, the address buffer 78 and data puff 78 are opened in response to the access permission signal IG, and access to the coexistence memory 5 is started. memory access 11i
An access control signal 3D is outputted from the control circuit 7 to the shared memory 5, data is outputted manually, and the access on the CPU-1 side of 1 is completed. Abnormality detection is performed by the memory foreign state detection circuit 6 using the access data at this time.

If an abnormality is detected, the CPU of 1 is activated by the detection signal 3C.
-1 is manually powered. 1) A failure during access to U-1 is manually generated by the IC as an interrupt, and -111 exception processing is performed.

When the cycle of the first CI'U-1 ends, the contention avoidance circuit 4 outputs an access permission signal 2D for the second CPU-2. This signal opens the address buffer 113 and data buffer 112 and starts accessing the shared memory 5. An access control signal 3D is output from the memory control circuit 7 to the shared memory 5, and data is output manually.

When the CPU-2 outputs the access request signal 2C, the wait control circuit 3 applies a weight 2E to itself. This wait 2E is canceled after the access permission signal 21) is output, but if the abnormality detection circuit G detects an abnormality in the access of CPU-2, it is not canceled and the wait 2E remains output. Therefore, 2C
l) U -2 increases the weight by g+/ until t of the abnormal cycle. Also, the abnormality detection signal when accessing CI 2) U-2 is sent from the wait control circuit 3 to CI 1) U.
Since the interrupt signal IF is output for -1, C of 1
I) U-1 performs processing for the failure and CI of 2)
It can be reset or stopped by the control signal IE for U-2.

Figure 3 shows the circuit of the weight control circuit 3.
-2 is the memory, and when it outputs the access request signal 2c, the NAND of 6 is inverted, clearing the flip-flop 1, and CP
When the access permission signal 2D of the CPU-2 is outputted from the 0M event avoidance circuit which outputs the wait signal 2E to U-2, the clearing of the 7-rip-flop 1 is canceled. Further, the clearing of counter 3 is also canceled. The first period counter 3 and the oscillator 4 are used to create a ready timing for accessing the memory, and at a preset time, they strike the clock of the flip-flop 1 and release the wait 2E for CI) U-2. However, if a memory failure occurs, the failure occurrence signal 3c causes the cycle to be transferred to the CPU.
-2 cycle, the flip-flop 2 is set by the NAND 8, and its output inputs an interrupt request IF to the CPU-1. Also, since the output of counter 8 is prohibited by AND7, the weight 2 of CI'U-2 is
E is not canceled; this weight is canceled by a control signal from the CPU-1, such as a reset.

FIG. 4 shows another system configuration in which the present invention is implemented in a multiprocessor system composed of a main processing unit and a slave processing unit. l is May/pu ``CI'U with 1 setsa''
-1 and 2 is the processor of the slave processing unit (CI) U -2
It is. 43 is the memory of the slave processing device, 44 is the slave processing Hn
This is Ilo. When the second CPU-2 accesses the memory 43, the memory 43 is accessed by the memory access control signal 42A, and at the same time, the wait control circuit 47 outputs the wait signal 42II to the second CI'U-2. The memory abnormality detection circuit 45 determines whether or not there is an abnormality in the memory access, and if there is no abnormality, the wait control circuit 47 releases the wait for CPU-2 of 2, and the CI of 2) U-2 is When the cycle is terminated, but a different IS is detected, the wait signal 4211 is not canceled and an interrupt signal 41B is inputted to CI'U-1 to notify the abnormality. 2 CPU-
When 2 accesses Ilo, the I10 access control signal 42D is used to access 110, and at the same time, the wait control circuit 47 sends a wait signal 4211 to the CPU-2 of 2.
Output. The I10 abnormality detection circuit 46 determines whether there is an abnormality in the I10 access, and if there is no abnormality, the wait control circuit 47 releases the wait for the CPU-2 of No. 2, and the CPU-2 of the No. 2 performs the I10 access cycle. However, if an abnormality is detected, the wait signal 42H is not canceled and an interrupt signal 4111 is input to the CPU-1 to notify the CPU-1 of the abnormality. This weight control circuit 47 is the same as in the ftE3 diagram.

〔Effect of the invention〕

As detailed above, according to the abnormality detection control method of the present invention, when a failure occurs in a multiprocessor system having a shared memory or a multiprocessor system consisting of a main processing unit and a slave processing unit, the abnormal cycle is suspended. Since the next cycle is not executed, the progress of the failure can be prevented, and the reliability of the system can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention.
A timing chart illustrating the access operation to the shared memory in the above embodiment, FIG. 3 shows the weight lli of the present invention.
The figure which shows an example of a control circuit. FIG. 4 is a block diagram showing another embodiment of the invention. 1...CPU 2...CPU 3...Wait control circuit and above Figure 3

Claims (1)

[Claims] In a multiprocessor in which at least two or more CPUs have a shared memory, when at least one of the processors accesses the shared memory, the CPU
1. An abnormality detection control method for a multiprocessor, characterized in that a wait state is applied to U, and when a memory abnormality detection circuit that checks errors in the shared memory detects an error, the wait state is continued.