JPS576956A - Information processor - Google Patents

Information processor

Info

Publication number
JPS576956A
JPS576956A JP8019680A JP8019680A JPS576956A JP S576956 A JPS576956 A JP S576956A JP 8019680 A JP8019680 A JP 8019680A JP 8019680 A JP8019680 A JP 8019680A JP S576956 A JPS576956 A JP S576956A
Authority
JP
Japan
Prior art keywords
circuits
memories
access
access request
latency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8019680A
Other languages
Japanese (ja)
Other versions
JPS6343775B2 (en
Inventor
Akira Ikuta
Masato Suyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP8019680A priority Critical patent/JPS576956A/en
Publication of JPS576956A publication Critical patent/JPS576956A/en
Publication of JPS6343775B2 publication Critical patent/JPS6343775B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To avoid the latency of fault, by securing a double structure for the common memory of a multiprocessor system and informing an error detected by either one of the two memories to a processor. CONSTITUTION:When an access request is given from processors 1-1-1-n, a priority selecting circuit 5-A of system A selects an access request. The selected access request is informed to interfaces 4A-1-4A-n and 4B-1-4B-n via cross circuits 11-A and 11-B. Then an access is given to common memories 3-A and 3-B according to the request signal sent from the selected processor. Both the address and the data receive a checking through parity checking circuits 9-A and 9-B. For instance, if an error is detected through the circuit 9-A of one side, an inhibition of access to the memories 3-A and 3-B is indicated to operation designating circuits 6-A and 6-B via cross circuits 10-A and 10-B. As a result, the latency can be avoided for a fault of the common memory of one side.
JP8019680A 1980-06-16 1980-06-16 Information processor Granted JPS576956A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8019680A JPS576956A (en) 1980-06-16 1980-06-16 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8019680A JPS576956A (en) 1980-06-16 1980-06-16 Information processor

Publications (2)

Publication Number Publication Date
JPS576956A true JPS576956A (en) 1982-01-13
JPS6343775B2 JPS6343775B2 (en) 1988-09-01

Family

ID=13711623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8019680A Granted JPS576956A (en) 1980-06-16 1980-06-16 Information processor

Country Status (1)

Country Link
JP (1) JPS576956A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63178397A (en) * 1987-01-20 1988-07-22 能美防災株式会社 Trouble monitor for disaster prevention equipment
JPS63251841A (en) * 1987-04-08 1988-10-19 Seiko Epson Corp Control method for detection of multi-processor abnormality
JPS63251840A (en) * 1987-04-08 1988-10-19 Seiko Epson Corp Control method for detection of multi-processor abnormality
EP2275939A1 (en) 2009-06-30 2011-01-19 Fujitsu Limited Processor and address translating method
JP2011081705A (en) * 2009-10-09 2011-04-21 Hitachi Ltd Memory control device and method for controlling the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040897A (en) * 1973-08-01 1975-04-14
JPS53104138A (en) * 1977-02-23 1978-09-11 Toshiba Corp Minicomputer composite system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5040897A (en) * 1973-08-01 1975-04-14
JPS53104138A (en) * 1977-02-23 1978-09-11 Toshiba Corp Minicomputer composite system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63178397A (en) * 1987-01-20 1988-07-22 能美防災株式会社 Trouble monitor for disaster prevention equipment
JPS63251841A (en) * 1987-04-08 1988-10-19 Seiko Epson Corp Control method for detection of multi-processor abnormality
JPS63251840A (en) * 1987-04-08 1988-10-19 Seiko Epson Corp Control method for detection of multi-processor abnormality
EP2275939A1 (en) 2009-06-30 2011-01-19 Fujitsu Limited Processor and address translating method
US8745356B2 (en) 2009-06-30 2014-06-03 Fujitsu Limited Processor and address translating method
JP2011081705A (en) * 2009-10-09 2011-04-21 Hitachi Ltd Memory control device and method for controlling the same

Also Published As

Publication number Publication date
JPS6343775B2 (en) 1988-09-01

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