JPS57133598A - System for write control of erroneous operation address - Google Patents

System for write control of erroneous operation address

Info

Publication number
JPS57133598A
JPS57133598A JP56019351A JP1935181A JPS57133598A JP S57133598 A JPS57133598 A JP S57133598A JP 56019351 A JP56019351 A JP 56019351A JP 1935181 A JP1935181 A JP 1935181A JP S57133598 A JPS57133598 A JP S57133598A
Authority
JP
Japan
Prior art keywords
erroneous operation
address
operation address
main storage
storage unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56019351A
Other languages
Japanese (ja)
Other versions
JPS6252339B2 (en
Inventor
Akiyoshi Kajiyama
Kazuyuki Shimizu
Hideo Iyota
Kiyoshi Oguri
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP56019351A priority Critical patent/JPS57133598A/en
Publication of JPS57133598A publication Critical patent/JPS57133598A/en
Publication of JPS6252339B2 publication Critical patent/JPS6252339B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation

Abstract

PURPOSE:To write an erroneous operation address in an erroneous operation address storage area of a main storage unit, by sending the erroneous operation address to a central processing device and sending it furthermore to a storage control unit when the erroneous operation occurs in the main storage unit. CONSTITUTION:If a fault occurs when a main storage unit 1 is accessed, a memory erroneous operation detecting part 5 of a storage control unit 2 sends the address of a storage position, where the fault occurs, as an erroneous operation address to a central processing device 3 through a buffer ineffective address bus. After a data block designated by the erroneous operation address is made ineffective, the erroneous operation address is set to a register, which holds exceptional addresses in address conversion, connected to a main storage bus. The erroneous operation address held in this register is stored in an erroneous operation address storage area 4 of the main storage unit 1 by the execution of an error processing sequence.
JP56019351A 1981-02-10 1981-02-10 System for write control of erroneous operation address Granted JPS57133598A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56019351A JPS57133598A (en) 1981-02-10 1981-02-10 System for write control of erroneous operation address

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56019351A JPS57133598A (en) 1981-02-10 1981-02-10 System for write control of erroneous operation address

Publications (2)

Publication Number Publication Date
JPS57133598A true JPS57133598A (en) 1982-08-18
JPS6252339B2 JPS6252339B2 (en) 1987-11-05

Family

ID=11996961

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56019351A Granted JPS57133598A (en) 1981-02-10 1981-02-10 System for write control of erroneous operation address

Country Status (1)

Country Link
JP (1) JPS57133598A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0113232A2 (en) * 1982-12-29 1984-07-11 Fujitsu Limited A machine check processing system
EP0141160A2 (en) * 1983-09-09 1985-05-15 Siemens Aktiengesellschaft Circuit arrangement for recording memory cell addresses containing errors
CN114780283A (en) * 2022-06-20 2022-07-22 新华三信息技术有限公司 Fault processing method and device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0113232A2 (en) * 1982-12-29 1984-07-11 Fujitsu Limited A machine check processing system
EP0141160A2 (en) * 1983-09-09 1985-05-15 Siemens Aktiengesellschaft Circuit arrangement for recording memory cell addresses containing errors
EP0141160A3 (en) * 1983-09-09 1987-10-21 Siemens Aktiengesellschaft Circuit arrangement for recording memory cell addresses containing errors
CN114780283A (en) * 2022-06-20 2022-07-22 新华三信息技术有限公司 Fault processing method and device
CN114780283B (en) * 2022-06-20 2022-11-01 新华三信息技术有限公司 Fault processing method and device

Also Published As

Publication number Publication date
JPS6252339B2 (en) 1987-11-05

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