JPS55122299A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS55122299A
JPS55122299A JP2950979A JP2950979A JPS55122299A JP S55122299 A JPS55122299 A JP S55122299A JP 2950979 A JP2950979 A JP 2950979A JP 2950979 A JP2950979 A JP 2950979A JP S55122299 A JPS55122299 A JP S55122299A
Authority
JP
Japan
Prior art keywords
data
memory
parity bit
unit
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2950979A
Other languages
Japanese (ja)
Inventor
Toshikatsu Watabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP2950979A priority Critical patent/JPS55122299A/en
Publication of JPS55122299A publication Critical patent/JPS55122299A/en
Pending legal-status Critical Current

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  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it possible to omit complicated operations even for change of memory contents in the data side, by using a memory element for error signal consisting of a RAM and by writing an error code to perform check.
CONSTITUTION: When power is supplied, data processing part 25 reads out only data of data storing memory elements 23-1W23-n, and sends it to the memory unit 21 side. At this time, check circuit 26 generates a parity bit according to this data and sends it to the unit 21 side. The unit 21 side writes only the parity bit out of transmitted data and the parity bit onto memory elements 24-1W24-n for error signal consisting of RAMs. After generation and write of the parity bit for all memory addresses, the control is transferred to the actual program to detect a parity error in circuit 26. As a result, even for change of memory contents in the data side, it is sufficient if data is read and the error code corresponding to this data is written.
COPYRIGHT: (C)1980,JPO&Japio
JP2950979A 1979-03-14 1979-03-14 Memory unit Pending JPS55122299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2950979A JPS55122299A (en) 1979-03-14 1979-03-14 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2950979A JPS55122299A (en) 1979-03-14 1979-03-14 Memory unit

Publications (1)

Publication Number Publication Date
JPS55122299A true JPS55122299A (en) 1980-09-19

Family

ID=12278057

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2950979A Pending JPS55122299A (en) 1979-03-14 1979-03-14 Memory unit

Country Status (1)

Country Link
JP (1) JPS55122299A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184656A (en) * 1982-04-22 1983-10-28 Nec Corp Program storage system
JPS59174642U (en) * 1983-05-10 1984-11-21 三菱電機株式会社 Memory abnormality detection circuit
JPS62109147A (en) * 1985-11-08 1987-05-20 Mitsubishi Electric Corp Detecting system for abnormality of random access memory

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58184656A (en) * 1982-04-22 1983-10-28 Nec Corp Program storage system
JPS59174642U (en) * 1983-05-10 1984-11-21 三菱電機株式会社 Memory abnormality detection circuit
JPS62109147A (en) * 1985-11-08 1987-05-20 Mitsubishi Electric Corp Detecting system for abnormality of random access memory

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