JPS55125600A - Checking method for read-only memory - Google Patents

Checking method for read-only memory

Info

Publication number
JPS55125600A
JPS55125600A JP3387579A JP3387579A JPS55125600A JP S55125600 A JPS55125600 A JP S55125600A JP 3387579 A JP3387579 A JP 3387579A JP 3387579 A JP3387579 A JP 3387579A JP S55125600 A JPS55125600 A JP S55125600A
Authority
JP
Japan
Prior art keywords
read
data
parity
rom10
word
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3387579A
Other languages
Japanese (ja)
Inventor
Jinichi Sakurai
Akio Takahashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3387579A priority Critical patent/JPS55125600A/en
Publication of JPS55125600A publication Critical patent/JPS55125600A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

PURPOSE: To ensure the accurate checking with every word in a high speed, by adding the read/wirte memory RAM to read-only memory ROM as the checking bit and then writing the error check information into RAM before use of ROM.
CONSTITUTION: Before execution of the program via the computer, the contents of ROM10 are read in sequence, and data 5 is supplied to parity bit generating circuit 20. Circuit 20 generates parity bit writing data 12 to be then written into RAM15 by writing command 14. Such action is given to each word of ROM10, and then the desired program is executed. As a result, data 5 along with parity reading data 13 are supplied to parity check circuit 30 for execution of the parity check. Thus the high-speed and accurate checking is given to the reading data of ROM10 with every word.
COPYRIGHT: (C)1980,JPO&Japio
JP3387579A 1979-03-22 1979-03-22 Checking method for read-only memory Pending JPS55125600A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3387579A JPS55125600A (en) 1979-03-22 1979-03-22 Checking method for read-only memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3387579A JPS55125600A (en) 1979-03-22 1979-03-22 Checking method for read-only memory

Publications (1)

Publication Number Publication Date
JPS55125600A true JPS55125600A (en) 1980-09-27

Family

ID=12398683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3387579A Pending JPS55125600A (en) 1979-03-22 1979-03-22 Checking method for read-only memory

Country Status (1)

Country Link
JP (1) JPS55125600A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833759A (en) * 1981-08-21 1983-02-28 Yamatake Honeywell Co Ltd Redundant code adding system
JPS59174642U (en) * 1983-05-10 1984-11-21 三菱電機株式会社 Memory abnormality detection circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5833759A (en) * 1981-08-21 1983-02-28 Yamatake Honeywell Co Ltd Redundant code adding system
JPS59174642U (en) * 1983-05-10 1984-11-21 三菱電機株式会社 Memory abnormality detection circuit

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