JPS5588154A - Data storage method - Google Patents

Data storage method

Info

Publication number
JPS5588154A
JPS5588154A JP15997278A JP15997278A JPS5588154A JP S5588154 A JPS5588154 A JP S5588154A JP 15997278 A JP15997278 A JP 15997278A JP 15997278 A JP15997278 A JP 15997278A JP S5588154 A JPS5588154 A JP S5588154A
Authority
JP
Japan
Prior art keywords
memory
address
bits
data
parity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15997278A
Other languages
Japanese (ja)
Inventor
Keiji Tsuchida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15997278A priority Critical patent/JPS5588154A/en
Publication of JPS5588154A publication Critical patent/JPS5588154A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To make it possible to read a data part and parity part at the same time without fail when reading character data, by effectively using a memory even when the number of bits constituting character data disagrees with that of bits of one address of a memory chip.
CONSTITUTION: Data memory 17 consists of four memory chips 19, 20, 21, and 22 and in each memory chip, one address is composed of four bits. On the other hand, parity memory 18 consists of memory chips 23 with one-address bit capacity of four bits, and when addresses A1, A2...An are assigned by an address counter, contents of respective addresses of memory chips 19W23 are read out at a time. For example, if address An is assigned, character data for four characters are transferred from memory chips 19W22 to data bit parts Dn, Dn+1... Dn+3 and parity bit parts are also read out.
COPYRIGHT: (C)1980,JPO&Japio
JP15997278A 1978-12-27 1978-12-27 Data storage method Pending JPS5588154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15997278A JPS5588154A (en) 1978-12-27 1978-12-27 Data storage method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15997278A JPS5588154A (en) 1978-12-27 1978-12-27 Data storage method

Publications (1)

Publication Number Publication Date
JPS5588154A true JPS5588154A (en) 1980-07-03

Family

ID=15705186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15997278A Pending JPS5588154A (en) 1978-12-27 1978-12-27 Data storage method

Country Status (1)

Country Link
JP (1) JPS5588154A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5917100U (en) * 1982-07-20 1984-02-01 株式会社明電舎 data writing device
WO1989000731A1 (en) * 1987-07-17 1989-01-26 Fanuc Ltd Memory device
EP0419863A2 (en) * 1989-09-29 1991-04-03 Texas Instruments Incorporated Multiple I/O select memory
JPH03156541A (en) * 1989-07-10 1991-07-04 Seiko Epson Corp Memory device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5917100U (en) * 1982-07-20 1984-02-01 株式会社明電舎 data writing device
WO1989000731A1 (en) * 1987-07-17 1989-01-26 Fanuc Ltd Memory device
JPH03156541A (en) * 1989-07-10 1991-07-04 Seiko Epson Corp Memory device
EP0419863A2 (en) * 1989-09-29 1991-04-03 Texas Instruments Incorporated Multiple I/O select memory
US5228132A (en) * 1989-09-29 1993-07-13 Texas Instrument Incorporated Memory module arranged for data and parity bits
EP0677849A3 (en) * 1989-09-29 1996-02-28 Texas Instruments Inc Multiple I/O select memory.

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