JPS5712498A - Integrated circuit device for memory - Google Patents

Integrated circuit device for memory

Info

Publication number
JPS5712498A
JPS5712498A JP8536380A JP8536380A JPS5712498A JP S5712498 A JPS5712498 A JP S5712498A JP 8536380 A JP8536380 A JP 8536380A JP 8536380 A JP8536380 A JP 8536380A JP S5712498 A JPS5712498 A JP S5712498A
Authority
JP
Japan
Prior art keywords
data
circuit
read
delivered
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8536380A
Other languages
Japanese (ja)
Other versions
JPS6031040B2 (en
Inventor
Hidehiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55085363A priority Critical patent/JPS6031040B2/en
Publication of JPS5712498A publication Critical patent/JPS5712498A/en
Publication of JPS6031040B2 publication Critical patent/JPS6031040B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing

Abstract

PURPOSE:To realize a high-speed test of an IC for memory, by installing a test data generating circuit, an address generating circuit plus a circuit that compares the read data with an expected value into an IC for memory. CONSTITUTION:A read/write control signal 105 is set in a writing state when a test state is read and written. Thus one of address decoding signals 300-3m0 is selected by an address decoding circuit 3, and a test data 403 is delivered from a write data buffer circuit 4 in the form of write data 210-21n to be written into designated cell groups i0-in. On the other hand, the signal 105 is set in a reading state, read data 200-20n are delivered from the cell groups i0-in to be supplied to a comparator 6 along with the data 403. The circuit 6 compares data 200-20n with an expected value data 403, and a comparison result signal 406 is delivered to show a coincidence or dissidence. The signal 406 is delivered as a read data 101 through a data buffer circuit 5.
JP55085363A 1980-06-24 1980-06-24 Integrated circuit device for memory Expired JPS6031040B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55085363A JPS6031040B2 (en) 1980-06-24 1980-06-24 Integrated circuit device for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55085363A JPS6031040B2 (en) 1980-06-24 1980-06-24 Integrated circuit device for memory

Publications (2)

Publication Number Publication Date
JPS5712498A true JPS5712498A (en) 1982-01-22
JPS6031040B2 JPS6031040B2 (en) 1985-07-19

Family

ID=13856622

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55085363A Expired JPS6031040B2 (en) 1980-06-24 1980-06-24 Integrated circuit device for memory

Country Status (1)

Country Link
JP (1) JPS6031040B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6238600A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Semiconductor memory device
EP0323438A2 (en) * 1984-07-18 1989-07-05 Hughes Aircraft Company Circuit and method for self-testing a memory in a gate array with a bidirectional symmetry

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0380940U (en) * 1989-12-12 1991-08-19

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0323438A2 (en) * 1984-07-18 1989-07-05 Hughes Aircraft Company Circuit and method for self-testing a memory in a gate array with a bidirectional symmetry
JPS6238600A (en) * 1985-08-14 1987-02-19 Fujitsu Ltd Semiconductor memory device
EP0213037A2 (en) * 1985-08-14 1987-03-04 Fujitsu Limited Semiconductor memory device having test pattern generating circuit

Also Published As

Publication number Publication date
JPS6031040B2 (en) 1985-07-19

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