JPS5712496A - Integrated circuit device for memory - Google Patents
Integrated circuit device for memoryInfo
- Publication number
- JPS5712496A JPS5712496A JP8536180A JP8536180A JPS5712496A JP S5712496 A JPS5712496 A JP S5712496A JP 8536180 A JP8536180 A JP 8536180A JP 8536180 A JP8536180 A JP 8536180A JP S5712496 A JPS5712496 A JP S5712496A
- Authority
- JP
- Japan
- Prior art keywords
- address
- memory
- circuit
- data
- read data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Abstract
PURPOSE:To realize an individual and high-speed test for an IC for memory, by providing an address generating circuit plus a circuit that compares the read data with an expected data into a memory IC. CONSTITUTION:When a test address signal 404 and an address control signal 400 are applied to an address decoding circuit 3 from a control circuit 1, one of address decoding signals 300-30mO is delivered to select one of memory cell groups iO-in(i=0,1-n). In the case of a writing action, an address signal 102 is delivered to write data 210-21n to be written into the cell groups iO-in. In the case of a reading action, read data 200-20n read out of the groups iO-in plus the signal 102, i.e., an expected value are supplied to a comparator 6. Then the result of coincidence or dissidence is supplied to a data buffer circuit 5 to be delivered by a read data control signal 401 and in the form of a read data 101.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8536180A JPS5712496A (en) | 1980-06-24 | 1980-06-24 | Integrated circuit device for memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8536180A JPS5712496A (en) | 1980-06-24 | 1980-06-24 | Integrated circuit device for memory |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5712496A true JPS5712496A (en) | 1982-01-22 |
Family
ID=13856564
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8536180A Pending JPS5712496A (en) | 1980-06-24 | 1980-06-24 | Integrated circuit device for memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5712496A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62298086A (en) * | 1986-05-07 | 1987-12-25 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | Integrated electronic memory circuit and electronic memory access system |
JPS6366799A (en) * | 1986-09-08 | 1988-03-25 | Toshiba Corp | Semiconductor memory device |
-
1980
- 1980-06-24 JP JP8536180A patent/JPS5712496A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62298086A (en) * | 1986-05-07 | 1987-12-25 | アドバンスト・マイクロ・ディバイシズ・インコ−ポレ−テッド | Integrated electronic memory circuit and electronic memory access system |
JPS6366799A (en) * | 1986-09-08 | 1988-03-25 | Toshiba Corp | Semiconductor memory device |
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