JPS5750380A - Writing method of buffer storage device - Google Patents

Writing method of buffer storage device

Info

Publication number
JPS5750380A
JPS5750380A JP55125029A JP12502980A JPS5750380A JP S5750380 A JPS5750380 A JP S5750380A JP 55125029 A JP55125029 A JP 55125029A JP 12502980 A JP12502980 A JP 12502980A JP S5750380 A JPS5750380 A JP S5750380A
Authority
JP
Japan
Prior art keywords
data
address
block
buffer memory
storage device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55125029A
Other languages
Japanese (ja)
Inventor
Mitsunobu Sugimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP55125029A priority Critical patent/JPS5750380A/en
Publication of JPS5750380A publication Critical patent/JPS5750380A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To realize the high-speed processing of data, by writing the subsequent blocks at one time into a buffer memory. CONSTITUTION:Circuits 1-9 form a buffer memory. In case the data requested from a CPU1 for reading does not exist in a buffer memory, an address of 20 bits (Nos. 0-19) of a subsequent block address register NAR17 is sent to a main storage device 12. Then the data of the block to which the above-mentioned address belongs is read, and a replacement control register 4 is inspected to detect the oldest block. The data of the subsequent blocks given from the device 12 are written into the block corresponding to a data array 7. The value of 12 bits (Nos. 0-11) of the NAR17 is written into an address array 2, and at the same time the maintenance is performed for the register 4.
JP55125029A 1980-09-09 1980-09-09 Writing method of buffer storage device Pending JPS5750380A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55125029A JPS5750380A (en) 1980-09-09 1980-09-09 Writing method of buffer storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55125029A JPS5750380A (en) 1980-09-09 1980-09-09 Writing method of buffer storage device

Publications (1)

Publication Number Publication Date
JPS5750380A true JPS5750380A (en) 1982-03-24

Family

ID=14900079

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55125029A Pending JPS5750380A (en) 1980-09-09 1980-09-09 Writing method of buffer storage device

Country Status (1)

Country Link
JP (1) JPS5750380A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003990A1 (en) * 1983-03-31 1984-10-11 Fanuc Ltd Memory readout control system
JPS615358A (en) * 1984-06-07 1986-01-11 Fujitsu Ltd Data processor
JPH03292548A (en) * 1990-04-11 1991-12-24 Koufu Nippon Denki Kk Information processor
JPH0668736B2 (en) * 1986-01-29 1994-08-31 ディジタル エクイプメント コ−ポレ−ション Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003990A1 (en) * 1983-03-31 1984-10-11 Fanuc Ltd Memory readout control system
JPS615358A (en) * 1984-06-07 1986-01-11 Fujitsu Ltd Data processor
JPH0361213B2 (en) * 1984-06-07 1991-09-19 Fujitsu Ltd
JPH0668736B2 (en) * 1986-01-29 1994-08-31 ディジタル エクイプメント コ−ポレ−ション Apparatus and method for providing a cache memory unit with a write operation utilizing two system clock cycles
JPH03292548A (en) * 1990-04-11 1991-12-24 Koufu Nippon Denki Kk Information processor

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