JPS5718074A - Buffer memory device - Google Patents
Buffer memory deviceInfo
- Publication number
- JPS5718074A JPS5718074A JP9220480A JP9220480A JPS5718074A JP S5718074 A JPS5718074 A JP S5718074A JP 9220480 A JP9220480 A JP 9220480A JP 9220480 A JP9220480 A JP 9220480A JP S5718074 A JPS5718074 A JP S5718074A
- Authority
- JP
- Japan
- Prior art keywords
- block
- block location
- data
- register
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
Abstract
PURPOSE:To simplify the sweep-out block determining means at new data registration, by setting the block location to the lowest priority with a block data at ineffective state. CONSTITUTION:A bus 103 includes address information indicating the block location to be ineffective and the data to the block location and they are set to a register 11. The block location information is inputted to an effective bit control circuit 13 with a bus 204 and set to a register 20 via a selection circuit 19. In a memory 14, the input data to the block location of the bus 204 is produced at the control circuit 13 for write-in processing, and the effective bit of the designated block location is reset. An LRU memory control circuit 22 produces the data to set the block to the lowest priority with the content of the register 20 for the renewal processing of the memory 23.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55092204A JPS605021B2 (en) | 1980-07-08 | 1980-07-08 | buffer memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP55092204A JPS605021B2 (en) | 1980-07-08 | 1980-07-08 | buffer memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5718074A true JPS5718074A (en) | 1982-01-29 |
JPS605021B2 JPS605021B2 (en) | 1985-02-07 |
Family
ID=14047911
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP55092204A Expired JPS605021B2 (en) | 1980-07-08 | 1980-07-08 | buffer memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS605021B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59140686A (en) * | 1983-01-31 | 1984-08-13 | Fujitsu Ltd | Control system of buffer memory |
JPS6043758A (en) * | 1983-08-20 | 1985-03-08 | Hitachi Ltd | Replace control system of buffer storage |
-
1980
- 1980-07-08 JP JP55092204A patent/JPS605021B2/en not_active Expired
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59140686A (en) * | 1983-01-31 | 1984-08-13 | Fujitsu Ltd | Control system of buffer memory |
JPS6043758A (en) * | 1983-08-20 | 1985-03-08 | Hitachi Ltd | Replace control system of buffer storage |
JPH0313616B2 (en) * | 1983-08-20 | 1991-02-22 | Hitachi Ltd |
Also Published As
Publication number | Publication date |
---|---|
JPS605021B2 (en) | 1985-02-07 |
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