JPS57209541A - Data processor having instruction rom - Google Patents
Data processor having instruction romInfo
- Publication number
- JPS57209541A JPS57209541A JP9491281A JP9491281A JPS57209541A JP S57209541 A JPS57209541 A JP S57209541A JP 9491281 A JP9491281 A JP 9491281A JP 9491281 A JP9491281 A JP 9491281A JP S57209541 A JPS57209541 A JP S57209541A
- Authority
- JP
- Japan
- Prior art keywords
- address
- correction
- instruction rom
- gate
- address register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
Abstract
PURPOSE:To add a plurality of instructions to correct a signal instruction on an instruction ROM, by providing a correction processing block to correct the contents of the instruction ROM. CONSTITUTION:Address information corresponding to an address area of an ROM1 read out from a memory 6 and the content of the address register 2 are compared at a comparison circuit 7. When they are coincident, gate circuits 11, 12, 14 and 15 are set and a gate circuit 13 is reset. When control information is provided, the readout of instructions after a plurality of times of correction is instructed. In this case, a branch address B is set to an address register 9 at correction via the gate 15. Accessing is made to a memory 8 with the contents of the address register 9 at correction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9491281A JPS57209541A (en) | 1981-06-19 | 1981-06-19 | Data processor having instruction rom |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9491281A JPS57209541A (en) | 1981-06-19 | 1981-06-19 | Data processor having instruction rom |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57209541A true JPS57209541A (en) | 1982-12-22 |
Family
ID=14123215
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9491281A Pending JPS57209541A (en) | 1981-06-19 | 1981-06-19 | Data processor having instruction rom |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57209541A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05143317A (en) * | 1991-11-18 | 1993-06-11 | Matsushita Electric Ind Co Ltd | Microcomputer |
-
1981
- 1981-06-19 JP JP9491281A patent/JPS57209541A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05143317A (en) * | 1991-11-18 | 1993-06-11 | Matsushita Electric Ind Co Ltd | Microcomputer |
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