JPS5530771A - Automatic correction and processing system for control memory error - Google Patents
Automatic correction and processing system for control memory errorInfo
- Publication number
- JPS5530771A JPS5530771A JP10360778A JP10360778A JPS5530771A JP S5530771 A JPS5530771 A JP S5530771A JP 10360778 A JP10360778 A JP 10360778A JP 10360778 A JP10360778 A JP 10360778A JP S5530771 A JPS5530771 A JP S5530771A
- Authority
- JP
- Japan
- Prior art keywords
- register
- error
- instruction
- control memory
- error detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To minimize the time delay, by performing the instruction interpretation processing by decoder group and the error detection processing by the error detection and correction circuit section parallelly.
CONSTITUTION: The microinstruction is stored in the control memory 1 in the form of error correction code given to it. Further, based on the instruction of the address register 2, it is read out from the memroy 1 to the data register 3, and the content of the register 3 is interpreted with the decoder group 4 to form the control instruction in the data processing unit. In parallel with the interpretation of instruction by the decoder group 4 in timing, the content of the register 3 is fed to the error detection and correction circuit 5 to detect and process error. Further, if any error is present, FF6 is set, and invalid signal is given to the AND circuits 11 and 12 via the fanout circuit 7. Further, correct microinstruction corrected at the circuit 5 is set to the register 3 via the gate.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53103607A JPS603219B2 (en) | 1978-08-25 | 1978-08-25 | Control memory error automatic correction processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53103607A JPS603219B2 (en) | 1978-08-25 | 1978-08-25 | Control memory error automatic correction processing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5530771A true JPS5530771A (en) | 1980-03-04 |
JPS603219B2 JPS603219B2 (en) | 1985-01-26 |
Family
ID=14358451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53103607A Expired JPS603219B2 (en) | 1978-08-25 | 1978-08-25 | Control memory error automatic correction processing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS603219B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57125448A (en) * | 1981-01-28 | 1982-08-04 | Nec Corp | Information processing device |
JPS60214043A (en) * | 1984-04-09 | 1985-10-26 | Fujitsu Ltd | Pipeline control circuit |
JPH0375834A (en) * | 1989-05-22 | 1991-03-29 | Tandem Comput Inc | Apparatus and method of sequentially correcting parity |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62158114U (en) * | 1986-03-31 | 1987-10-07 |
-
1978
- 1978-08-25 JP JP53103607A patent/JPS603219B2/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57125448A (en) * | 1981-01-28 | 1982-08-04 | Nec Corp | Information processing device |
JPS6258023B2 (en) * | 1981-01-28 | 1987-12-03 | Nippon Electric Co | |
JPS60214043A (en) * | 1984-04-09 | 1985-10-26 | Fujitsu Ltd | Pipeline control circuit |
JPH0375834A (en) * | 1989-05-22 | 1991-03-29 | Tandem Comput Inc | Apparatus and method of sequentially correcting parity |
Also Published As
Publication number | Publication date |
---|---|
JPS603219B2 (en) | 1985-01-26 |
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