JPS5530771A - Automatic correction and processing system for control memory error - Google Patents

Automatic correction and processing system for control memory error

Info

Publication number
JPS5530771A
JPS5530771A JP10360778A JP10360778A JPS5530771A JP S5530771 A JPS5530771 A JP S5530771A JP 10360778 A JP10360778 A JP 10360778A JP 10360778 A JP10360778 A JP 10360778A JP S5530771 A JPS5530771 A JP S5530771A
Authority
JP
Japan
Prior art keywords
register
error
instruction
control memory
error detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10360778A
Other languages
Japanese (ja)
Other versions
JPS603219B2 (en
Inventor
Takashi Aoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53103607A priority Critical patent/JPS603219B2/en
Publication of JPS5530771A publication Critical patent/JPS5530771A/en
Publication of JPS603219B2 publication Critical patent/JPS603219B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To minimize the time delay, by performing the instruction interpretation processing by decoder group and the error detection processing by the error detection and correction circuit section parallelly.
CONSTITUTION: The microinstruction is stored in the control memory 1 in the form of error correction code given to it. Further, based on the instruction of the address register 2, it is read out from the memroy 1 to the data register 3, and the content of the register 3 is interpreted with the decoder group 4 to form the control instruction in the data processing unit. In parallel with the interpretation of instruction by the decoder group 4 in timing, the content of the register 3 is fed to the error detection and correction circuit 5 to detect and process error. Further, if any error is present, FF6 is set, and invalid signal is given to the AND circuits 11 and 12 via the fanout circuit 7. Further, correct microinstruction corrected at the circuit 5 is set to the register 3 via the gate.
COPYRIGHT: (C)1980,JPO&Japio
JP53103607A 1978-08-25 1978-08-25 Control memory error automatic correction processing method Expired JPS603219B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53103607A JPS603219B2 (en) 1978-08-25 1978-08-25 Control memory error automatic correction processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53103607A JPS603219B2 (en) 1978-08-25 1978-08-25 Control memory error automatic correction processing method

Publications (2)

Publication Number Publication Date
JPS5530771A true JPS5530771A (en) 1980-03-04
JPS603219B2 JPS603219B2 (en) 1985-01-26

Family

ID=14358451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53103607A Expired JPS603219B2 (en) 1978-08-25 1978-08-25 Control memory error automatic correction processing method

Country Status (1)

Country Link
JP (1) JPS603219B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57125448A (en) * 1981-01-28 1982-08-04 Nec Corp Information processing device
JPS60214043A (en) * 1984-04-09 1985-10-26 Fujitsu Ltd Pipeline control circuit
JPH0375834A (en) * 1989-05-22 1991-03-29 Tandem Comput Inc Apparatus and method of sequentially correcting parity

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62158114U (en) * 1986-03-31 1987-10-07

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57125448A (en) * 1981-01-28 1982-08-04 Nec Corp Information processing device
JPS6258023B2 (en) * 1981-01-28 1987-12-03 Nippon Electric Co
JPS60214043A (en) * 1984-04-09 1985-10-26 Fujitsu Ltd Pipeline control circuit
JPH0375834A (en) * 1989-05-22 1991-03-29 Tandem Comput Inc Apparatus and method of sequentially correcting parity

Also Published As

Publication number Publication date
JPS603219B2 (en) 1985-01-26

Similar Documents

Publication Publication Date Title
JPS5530771A (en) Automatic correction and processing system for control memory error
JPS5555499A (en) Memory control unit
JPS5487145A (en) Display system for data comparison and agreement
JPS5259537A (en) Data processor
JPS5447540A (en) Fault correction system for control memory
JPS5622291A (en) Bit error correction method for memory
JPS5452936A (en) Memroy processor
JPS57209541A (en) Data processor having instruction rom
JPS5543658A (en) Control system for microorder execution
JPS5485649A (en) Microprogram control unit
JPS5552598A (en) Data processor
JPS55124806A (en) Sequencing circuit of microcomputer
JPS5525192A (en) Illegal processing system for option instruction
JPS573156A (en) Central processing device
JPS56135242A (en) Program correcting circuit
JPS57199052A (en) Data processing device
JPS5595152A (en) Microinstruction execution control system
JPS5696336A (en) Processing system for multilayer level microprogram
JPS567126A (en) Initializing system
JPS56127248A (en) Operation controller
JPS54141530A (en) Information processor
JPS54104751A (en) Data processor
JPS55162156A (en) Data processor
JPS5782296A (en) Detection circuit for memory incorrect access program
JPS55146681A (en) Buffer memory correction system