JPS54141530A - Information processor - Google Patents

Information processor

Info

Publication number
JPS54141530A
JPS54141530A JP4949678A JP4949678A JPS54141530A JP S54141530 A JPS54141530 A JP S54141530A JP 4949678 A JP4949678 A JP 4949678A JP 4949678 A JP4949678 A JP 4949678A JP S54141530 A JPS54141530 A JP S54141530A
Authority
JP
Japan
Prior art keywords
error
data
main memory
parity error
causing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4949678A
Other languages
Japanese (ja)
Inventor
Hideo Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP4949678A priority Critical patent/JPS54141530A/en
Publication of JPS54141530A publication Critical patent/JPS54141530A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To enable the continuity of processing and the point out of the error position, by reading out correct data from the main memory immediately after the parity error is caused in the high speed buffer memory.
CONSTITUTION: When the parity error is detected in the buffer memory, the error flip flop 13 is set. Further, the instruction counter 19 is set to the address causing parity error at this time. Next, the address causing error data from the main memory is fetched by referencing the instruction counter. The data from the main memory is outputted to the bus 10 and the content is compared with the data causing the parity error at the comparison circuit 6. The result compared in bit correspondence is set and displayed on the error display register 17. Simultaneously, the error flip flop is reset and the instruction sequence is executed.
COPYRIGHT: (C)1979,JPO&Japio
JP4949678A 1978-04-25 1978-04-25 Information processor Pending JPS54141530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4949678A JPS54141530A (en) 1978-04-25 1978-04-25 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4949678A JPS54141530A (en) 1978-04-25 1978-04-25 Information processor

Publications (1)

Publication Number Publication Date
JPS54141530A true JPS54141530A (en) 1979-11-02

Family

ID=12832747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4949678A Pending JPS54141530A (en) 1978-04-25 1978-04-25 Information processor

Country Status (1)

Country Link
JP (1) JPS54141530A (en)

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