JPS56135242A - Program correcting circuit - Google Patents

Program correcting circuit

Info

Publication number
JPS56135242A
JPS56135242A JP3697780A JP3697780A JPS56135242A JP S56135242 A JPS56135242 A JP S56135242A JP 3697780 A JP3697780 A JP 3697780A JP 3697780 A JP3697780 A JP 3697780A JP S56135242 A JPS56135242 A JP S56135242A
Authority
JP
Japan
Prior art keywords
program
signal
circuit
rom
switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3697780A
Other languages
Japanese (ja)
Inventor
Tadashi Nishijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3697780A priority Critical patent/JPS56135242A/en
Publication of JPS56135242A publication Critical patent/JPS56135242A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/268—Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE:To correct even a program composed of ROM as well by the program correcting circuit of a computer, by interrupting the computer and then by executing a program newly corrected in interruption processing. CONSTITUTION:Decoder 7 selects RAM3, ROM4 and input-output circuit 5 connected to data bus 2 of CPU1 to execute a program. The program correcting circuit, encircled with dotted line 8, consists of switch 9 for setting optionally an address where the program is corrected, and coincidence detecting circuit 12 which compares set signal 100 generated with switch 9 with signal 101 from cpul. When the coincidence between an address set with switch 9 and that of the memory is detected, circuit 8 outputs memory inhibition signal 102 to decoder 7 to inhibit a read of ROM and generate interruption signal 103 to CPU1 simultaneously. Thus, even a program composed of ROM is corrected.
JP3697780A 1980-03-25 1980-03-25 Program correcting circuit Pending JPS56135242A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3697780A JPS56135242A (en) 1980-03-25 1980-03-25 Program correcting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3697780A JPS56135242A (en) 1980-03-25 1980-03-25 Program correcting circuit

Publications (1)

Publication Number Publication Date
JPS56135242A true JPS56135242A (en) 1981-10-22

Family

ID=12484808

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3697780A Pending JPS56135242A (en) 1980-03-25 1980-03-25 Program correcting circuit

Country Status (1)

Country Link
JP (1) JPS56135242A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58109946A (en) * 1981-12-23 1983-06-30 Yamatake Honeywell Co Ltd Debugging method for program
JPS60209805A (en) * 1984-04-03 1985-10-22 Fuji Xerox Co Ltd Maintenance control system of copying machine or the like

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58109946A (en) * 1981-12-23 1983-06-30 Yamatake Honeywell Co Ltd Debugging method for program
JPS60209805A (en) * 1984-04-03 1985-10-22 Fuji Xerox Co Ltd Maintenance control system of copying machine or the like

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