JPS5485649A - Microprogram control unit - Google Patents

Microprogram control unit

Info

Publication number
JPS5485649A
JPS5485649A JP15393077A JP15393077A JPS5485649A JP S5485649 A JPS5485649 A JP S5485649A JP 15393077 A JP15393077 A JP 15393077A JP 15393077 A JP15393077 A JP 15393077A JP S5485649 A JPS5485649 A JP S5485649A
Authority
JP
Japan
Prior art keywords
circuit
microprogram
readout
processing
error
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15393077A
Other languages
Japanese (ja)
Inventor
Takao Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15393077A priority Critical patent/JPS5485649A/en
Publication of JPS5485649A publication Critical patent/JPS5485649A/en
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To increase the reliability and processing speed, by improving the lowering in the number of processing steps in a given time, through the classification of microprogram instructions into those in which the delay in the execution time is a problem and those not a problem.
CONSTITUTION: The unit consists of the microprogram memory 101, address register 102, circuit 104 correcting the readout of the memory 101 according to the output of the circuit 103, microprogram instruction register 105,FF 106, error processing circuit 107, interpreting means 108, FF109, inhibit gate 151, AND gates 152 to 154. When FF109 is "1", if readout error is detected 103 at the readout of the microprogram instruction, suitable processing is made even if an output is given to the circuit 107 via the gate 153. Otherwise, if readout error, processing is executed while correcting it with the correction circuit 104.
COPYRIGHT: (C)1979,JPO&Japio
JP15393077A 1977-12-20 1977-12-20 Microprogram control unit Pending JPS5485649A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15393077A JPS5485649A (en) 1977-12-20 1977-12-20 Microprogram control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15393077A JPS5485649A (en) 1977-12-20 1977-12-20 Microprogram control unit

Publications (1)

Publication Number Publication Date
JPS5485649A true JPS5485649A (en) 1979-07-07

Family

ID=15573179

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15393077A Pending JPS5485649A (en) 1977-12-20 1977-12-20 Microprogram control unit

Country Status (1)

Country Link
JP (1) JPS5485649A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121540A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Operation control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59121540A (en) * 1982-12-28 1984-07-13 Fujitsu Ltd Operation control system

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