JPS56127248A - Operation controller - Google Patents

Operation controller

Info

Publication number
JPS56127248A
JPS56127248A JP3053280A JP3053280A JPS56127248A JP S56127248 A JPS56127248 A JP S56127248A JP 3053280 A JP3053280 A JP 3053280A JP 3053280 A JP3053280 A JP 3053280A JP S56127248 A JPS56127248 A JP S56127248A
Authority
JP
Japan
Prior art keywords
signal
delivered
access
chip
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3053280A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Fumitaka Sato
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3053280A priority Critical patent/JPS56127248A/en
Priority to EP81101194A priority patent/EP0036093B1/en
Priority to DE8181101194T priority patent/DE3176840D1/en
Priority to DE8484105306T priority patent/DE3177096D1/en
Priority to US06/236,116 priority patent/US4616331A/en
Priority to EP84105306A priority patent/EP0139080B1/en
Publication of JPS56127248A publication Critical patent/JPS56127248A/en
Priority to US06/886,807 priority patent/US4734849A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3812—Instruction prefetching with instruction modification, e.g. store into instruction stream
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
  • Advance Control (AREA)

Abstract

PURPOSE:To generate an interruption of an illegal address in a correct timing at all times for an operation controller having an instruction prefetching buffer formed into a chip, by using a specified signal showing the correctness/incorrectness of access when an access is given to the main memory. CONSTITUTION:In the memory address transfer mode under which the 1-chip CPU101 gives an access to the main memory to carry out a prefetching of an instruction, no control signal ROE is delivered with the memory address signal being delivered. Thus the phasical block error (PBE) signal of a bit is delivered from the conversion table 105T to be applied to TEST1. The PBE signal is then taken into the 1-chip CPU in the microinstruction reading cycle after the transfer of the memory address and along with the microinstruction plus the external signal group of other TEST1. Thus the PEB signal corresponding to the prefetched instruction word can always hold a corresponding relation. As a result, an interruption of an illegal address can be produced in a correct timing at all times.
JP3053280A 1980-02-25 1980-03-11 Operation controller Pending JPS56127248A (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
JP3053280A JPS56127248A (en) 1980-03-11 1980-03-11 Operation controller
EP81101194A EP0036093B1 (en) 1980-02-25 1981-02-19 An information-processing system consisting of an arithmetic control unit into a one-chip type by application of a highly-integrated semiconductor device
DE8181101194T DE3176840D1 (en) 1980-02-25 1981-02-19 An information-processing system consisting of an arithmetic control unit into a one-chip type by application of a highly-integrated semiconductor device
DE8484105306T DE3177096D1 (en) 1980-02-25 1981-02-19 An information-processing system
US06/236,116 US4616331A (en) 1980-02-25 1981-02-19 Information processing system consisting of an arithmetic control unit formed into a one-chip typed by application of a highly-integrated semiconductor device
EP84105306A EP0139080B1 (en) 1980-02-25 1981-02-19 An information-processing system
US06/886,807 US4734849A (en) 1980-02-25 1986-07-16 Information-processing system having a single chip arithmetic control unit with means for prefetching instructions

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3053280A JPS56127248A (en) 1980-03-11 1980-03-11 Operation controller

Publications (1)

Publication Number Publication Date
JPS56127248A true JPS56127248A (en) 1981-10-05

Family

ID=12306400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3053280A Pending JPS56127248A (en) 1980-02-25 1980-03-11 Operation controller

Country Status (1)

Country Link
JP (1) JPS56127248A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943447A (en) * 1982-09-03 1984-03-10 Hitachi Ltd Data processor
JPH061441B2 (en) * 1983-09-12 1994-01-05 モトロ−ラ・インコ−ポレ−テツド Preliminary confirmation device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5943447A (en) * 1982-09-03 1984-03-10 Hitachi Ltd Data processor
JPH061441B2 (en) * 1983-09-12 1994-01-05 モトロ−ラ・インコ−ポレ−テツド Preliminary confirmation device

Similar Documents

Publication Publication Date Title
JPS55129847A (en) Access system of memory unit
JPS57123455A (en) Instruction executing device
JPS56127248A (en) Operation controller
JPS5744294A (en) Alternating memory control system
JPS5781675A (en) Electronic tabulating computer
JPS57109055A (en) Readout control system for microinstruction
JPS575157A (en) Extension system for branch address of microinstruction
JPS54109333A (en) Main memory unit
JPS5681490A (en) Week programmer
JPS57143800A (en) Storage device
JPS5379329A (en) Test method of memory circuit
JPS5631143A (en) Preventing system for program runaway
JPS5683889A (en) Error correcting system
JPS55163677A (en) Memory read control system
JPS5475231A (en) Buffer memory control system
JPS57193847A (en) Memory bank dividing circuit
JPS57100540A (en) Microprogram controller
JPS578999A (en) Memory controller
JPS5370729A (en) Memory unit
JPS5698A (en) Partial write-in system for memory device
JPS55118163A (en) Memory device
JPS5688550A (en) Pseudo error transmission system
JPS5755464A (en) Storage control device
JPS5687299A (en) Memory device control system
JPS54158136A (en) Data processor