JPS54158136A - Data processor - Google Patents

Data processor

Info

Publication number
JPS54158136A
JPS54158136A JP6678278A JP6678278A JPS54158136A JP S54158136 A JPS54158136 A JP S54158136A JP 6678278 A JP6678278 A JP 6678278A JP 6678278 A JP6678278 A JP 6678278A JP S54158136 A JPS54158136 A JP S54158136A
Authority
JP
Japan
Prior art keywords
data
error
correction
memory
correct
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6678278A
Other languages
Japanese (ja)
Inventor
Yoichi Okada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6678278A priority Critical patent/JPS54158136A/en
Publication of JPS54158136A publication Critical patent/JPS54158136A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To reduce the loss time of the processing by cancelling once the execution time storing the error data and then storing the correct data for continuation of the data process.
CONSTITUTION: The data necessary for process is read out of memory unit 1 and then stored into memory data register 2 through reading data bus (a) and memory data selector 3. When the bit error is detected to the data at error detection circuit 6, correction control signal (A) is applied to error correction circuit 7 and clock control circuit 8. With indication of signal (A), the correction of the error bit is given to the data of memory reading register 4. Thus, the correct data is sent to correction data bus 6. At the same time, the processing is retarded by one time for clock control circuit 8 received the error control signal in order to store again the correct reading data after correction into the memory data register.
COPYRIGHT: (C)1979,JPO&Japio
JP6678278A 1978-06-05 1978-06-05 Data processor Pending JPS54158136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6678278A JPS54158136A (en) 1978-06-05 1978-06-05 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6678278A JPS54158136A (en) 1978-06-05 1978-06-05 Data processor

Publications (1)

Publication Number Publication Date
JPS54158136A true JPS54158136A (en) 1979-12-13

Family

ID=13325772

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6678278A Pending JPS54158136A (en) 1978-06-05 1978-06-05 Data processor

Country Status (1)

Country Link
JP (1) JPS54158136A (en)

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