JPS59140686A - Control system of buffer memory - Google Patents

Abstract

PURPOSE:To ensure an application of a region related to the update of data of a main memory by another information processor with high efficiency, by dividing the display of an address on a main memory into upper and lower digits and providing plural sets of buffer memories having addresses of the same number as those which can be indicated by said lower digits of the address. CONSTITUTION:When an address (b<2>) is set to an address register 4'', (b) exists in the entry of an address 2 of an index register 9'. Therefore the contents of the address 2 of a buffer memory 8' corresponding to the (b) correspond to ''LM'', and the corresponding validity display bit is set at ''0''. In addition, if the bit corresponding to the address 2 of a register 10 is set at ''0'', this bit is rewritten to ''1''. As a result, the data of a main memory 6'' are loaded to the entry of the address 2 of the memory 8' when the next loading is carried out to the address 2. Thus the entry data of the address 2 of the memory 8' remains.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a system in which a main memory is shared by a plurality of information processing devices, and when one information processing device updates data in the main memory, other information The present invention relates to efficient control of the buffer memory related to processing for invalidating unupdated data when the processing device retains the data in its own buffer memory.

(2) Background of the Technology Information processing devices are generally required to have high speeds in reading and writing data from a storage unit and large storage capacity. In order to meet these conditions and realize an economical device, a high-speed, relatively small-capacity buffer memory is provided inside the information processing device in addition to the large-capacity main memory, and the data in the main memory is stored at a certain level. Some devices employ a method of loading each area into the buffer memory and performing processing. According to this method, the number of accesses to the relatively slow main memory is reduced, and processing speed can be increased.

On the other hand, for the purpose of improving system reliability and processing speed, or for a special system type, a system configuration may be adopted in which a plurality of information processing apparatuses share a main memory to perform processing. If such a system configuration is adopted using information processing devices having the buffer memory, when one information processing device updates data on the main memory, another information processing device has already updated the data in its own buffer memory. If you keep it in your account and use it without knowing that it has been updated, it will cause inconvenience.

Therefore, when data in a storage device is updated, its address is sent to another information processing device, which invalidates the data in that area if it is already in the buffer memory of that information processing device. Measures may be taken, such as updating the data or rewriting it with new data.

(3) Prior art and problems FIG. 1 is a block diagram showing an example of conventional buffer memory control, in which 1 is an information processing device, 2 is a buffer memory, 3 is an index memory, 4 is an address register,
Reference numeral 5 represents a storage device, 6 a main memory, and 7 a connection to other information processing devices.

In FIG. 1, the main memory 6 has a certain area (AAX in the figure).
0.1 for each section containing data such as BB.
Addresses such as 2 to n are assigned.

The buffer memory 2 has a plurality of areas of the same size as the fixed area of the main memory 6, and as shown in the figure,
Address (0 to n) for each area (hereinafter referred to as entry)
) is attached.

Since the index memory 5 corresponds to the buffer memory 2, it has the same number of entries with the same addresses as the buffer memory 2.

Each entry has a validity indicator bit (d=N) that determines whether the entry in the buffer memory with the corresponding address is valid (represented by 11") or invalid (represented by NO4), and a main memory 6 Address for each fixed area (
It has an area with the number of bits necessary to display (0 to n).

When the information processing device 1 reads data at a certain address from the storage device 5, it first checks the index memory 5 to check whether the address exists and whether the data is valid. , if the validity is displayed (determined), the data written in the entry in the buffer memory 2 at the same address as the entry in the index memory 5 where the address exists as data is read.

When checking index memory 5, if the corresponding address does not exist or is displayed as invalid,
Access the main memory 6, read the data at the corresponding address, and put the data into an empty entry (an entry whose validity is not displayed) on the buffer memory 2. An entry in the index memory 3 having the same address as the entry Write the corresponding address in the main memory 6 to the IJ.If there is no free IJ, the IJ is rewritten sequentially starting from the first address (0 address) even if it is valid.

When the contents of the main memory 6 are updated by another information processing device or the like, the corresponding address of the main memory 6 is set in the address register 4. When the value of the address is in any entry of the index memory 5 and it is displayed as valid, the validity indicator bit (a) of the entry is set to 10''.

This method has the disadvantage that the processing speed is slow because it is necessary to search many entries in order to search for the corresponding address in the index memory 3.

FIG. 2 is a block diagram showing another example of conventional backup memory control, and 1' to 7' are the same as 1 to 7 in FIG.

In Fig. 2, the main memory 6' has a certain area (one section containing data such as AB in the figure).KaO1a+...
I have an address such as...

The backup memory 2' has a plurality of entries of the same size as the fixed size area of the main memory 6', and as shown in the figure, each entry is assigned an address from 0 to n. There is.

Addresses 0 to n are lower addresses such as address aO1a+ for each area of a certain size in the main memory 6', and therefore the number of entries on the backup memory 2' and the address n are as follows: It is determined by the number of bits of the lower address. (For example, if it is 6 bits, there are 64 entries, and the addresses are 0 to 65.) Index memory 5' corresponds to buffer memory 2', and stores the same number of entries with the same addresses as backup memory 2'. have.

For each entry, the content of the entry in the memory 2' that has the corresponding address is valid (11 or invalid (validity display pit value indicating whether it is 0)), and the content of the entry in the main memory 6' is Upper addresses of a certain size area (a, b
It has an area with the number of bits necessary to display the data (Xe, etc.).

When the information processing device 1' needs data in the main memory 6', it first checks the entry in the index memory 3' whose address is the same as the lower address of the area where the data exists, and then determines the upper address of the area. If the entry exists and the validity indicating pit is ``1'', data is read from the entry in the buffer memory 2' corresponding to the entry and used.

When the information processing device 1' checks the index memory 3' and finds that the necessary data does not exist in the buffer memory 2', the information processing device 1' accesses the main memory 6' and reads the area containing the data. This is written to the entry of the backup memory 2' having the same value as the lower address of the area, and the value of the upper address of the area is written to the entry of the index memory 5' corresponding to the entry of the buffer memory 2'. Write to the validity indicator bit (
B) to 1".

When another information processing device updates the contents of the memory 6', the address is sent to the address register 4.
’. If the upper (b) of the address exists in the entry having the same address as the lower (c) of the address in the index memory 5', the validity indicating bit (a) is set to 10''.

Programs and data may be arranged similar to each other at fixed address intervals due to program address modification, and the same area at lower addresses with different upper addresses may be continuously used, but in such cases, This method has a problem in that efficient buffering cannot be performed.

(4) Purpose of the Invention It is an object of the present invention to provide a control method that has a high probability of making use of an area related to main memory data updated by another information processing device.

(5) Structure and object of the invention According to the present invention, as described in the claims, the main memory is shared with another information processing device, the data in the main memory is loaded into the buffer memory, and the data in the main memory is loaded into the buffer memory. In an information processing device that performs processing by accessing a buffer memory, the display of an address on the main memory is divided into high-order digits and low-order digits, and a plurality of sets of buffer 7 memories are provided with the same number of addresses TW as can be indicated by the low-order digits. , a pit that displays the validity of the contents of each address of the buffer memory, and an index memory that corresponds to the buffer memory and displays the upper digits of the main memory with the same number of sets as the buffer memory;
A register is provided to instruct one set of areas at the same address in the plurality of buffer memories to which main memory data should be loaded next, and the main memory data already held at a specific address in the buffer memory is loaded. This is achieved by a buffer memory control method characterized in that when the other information processing capacity is replaced, the register specifies the buffer memory at the specific address.

(6) Embodiment of the invention FIG. 5 is a block diagram showing one embodiment of the invention.
' and 4'' to 7'' are the same as 1 and 4 to 7 in FIG. 1, 8.8' is a buffer memory, 9.9' is an index memory, and TO is a register.

In Fig. 5, the main menu 6'' is an area of a certain size (
LOX for each block containing data such as AB in the diagram)
&j...I have the address of the song, etc.

The buffer memory 8 has a plurality of entries of the same size as the fixed size area of the main memory 6'', and as shown in the figure, each entry is assigned an address of 0 to n. .

The addresses 0 to n are the addresses IL0, 14, etc. for each area of a certain size in the main memory 6, and are the lower order addresses of songs, etc. Therefore, the number of entries on the buffer memory B and the address n are the lower addresses of the addresses IL0, 14, etc. for each area of a certain size in the main memory 6. Determined by the number of bits. (For example, if it is 6 bits, there are 64 entries,
The address will be 0 to 63) Buffer memory 8/%
The same is true.

Index memory 9 corresponds to buffer memory 8 and has the same number of entries with the same addresses as buffer memory 8.

Each entry indicates whether the contents of the backup memory entry with the corresponding address are valid (11”) or invalid (1”).
0"), and the upper addresses (a, b) of a certain size area of the main memory 6'.
, c... songs, etc.) has an area with the number of bits necessary for vertical display.

Index memory 9' corresponds to buffer memory 8', and its contents are exactly the same as those of index memory 9 described above.

Register 10 has M bits corresponding to each entry in index memory 9.9', which is SS O//
If so, it means that the next data to be loaded from main memory 6# is the buffer memory 8 entry, and if it is 11", it is the backup memory 8' entry. (Always 2 entries) IJ When another information processing device, etc. updates the data in the main memory 6, the register 4 is used to store the address of that area, and the upper address is ( (b), the lower address is (c)
can be placed in

When the information processing device 1 "needs data in the main memory 6", first, it checks the entry with the same address as the lower address of the area where the data exists in the index memo I79.9', and finds the address of the area. If a higher order exists and the validity indicating bit is vk+'', data is read from the entry in the buffer memory 8.8' corresponding to the entry f'C and used.

When the information processing device 1# checks the index memory 9.9' and finds that the necessary data does not exist in the backup memory 8.8', it accesses the main memory 6'',
The area containing the data is read and loaded into the buffer memory 8 or 8'. At this time, buffer memory 8 or 8 having the same address as the lower address of the area
If the corresponding pit in the register 10 is an ant 0" in any entry of ', the buffer memory 8 is used, and if the corresponding pit is an ant 11", the buffer memory 8' is used.

When the contents of the main memory 6'' are updated by another information processing device, etc., the address of that area is updated in the address register 4.
''.The entry in index memory 9 or 9' that has the same value as the lower address (c) of the address is stored with the upper address (opening) of the address set in address register 4'', and is valid. Gender indication bitch membrane 1
If it is '1', the fingerprint data exists in the backup memory, so the validity indication bit (() 會ゝゝ[1
11CL, to prevent the data from being used incorrectly.

For example, when address b2 is set in address register 4'' in Figure 3, b exists in the entry at address 2 in index register 9', so the contents of address 2 in buffer memory B' correspond Since 'LM' is applicable, its validity indicator bit is set to t-'0.

Furthermore, at this time, if the bit corresponding to address 2 of the register 10 is 0'', it is rewritten to 11''.

As a result, the data in the main memory 6'' will be loaded into the entry at address 2 in the buffer memory 8' at the next load to address 2, so the data in the entry at address 2 in the backup memory 8 will remain. .

(7) Effects of the Invention As explained in detail above, according to the method of the present invention, the main memory is shared with other information processing devices, and the data in the main memory is stored in a buffer of a certain size. In an information processing device that loads data into memory and processes it by accessing the backup memory, it is usually equipped with two sides of buffer memory and index memory, and a register to instruct which side to use. Control is performed so that the display of the register is alternately rewritten so that new data is loaded into the loaded side, and when another information processing device etc. updates the data in the main memory, the data is stored in the buffer. Since it was held in memory, when it is invalidated, the IJ side of the buffer memory is rewritten to be used the next time, regardless of the alternating nature of the register contents, so it cannot be used by other information processing devices, etc. , even when the data in the main memory is updated, it has the same lower address and the different data at the higher address remains, so it has the advantage that the probability that the data exists in the buffer memory is high, and the effect is great. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one example of conventional buffer memory control, FIG. 2 is a block diagram showing another example of conventional backup memory control, and FIG. 3 is a block diagram showing one embodiment of the present invention. . 1.1', 1'... Information processing device, 2.2'... Buffer memory, 5.5'... Index memory, 4
．． 4', 4"...address register, 5.5', 5"...
・Storage device, 6.6', 6''...Main memory, 7.7'
, 7"...Connection to other information processing devices, 8.8'...
・Buffer memory, 9.9'... Index memory, 1゜... Register, (a)... Validity display bit, (b)... Upper address, e→... Lower address 1 Figure W-3 Figure Gool

Claims (1)

[Claims] In an information processing device that shares main memory with another information processing device, loads data in the main memory to a backup memory, and accesses the backup memory to perform processing, addresses on the main memory are displayed as upper digits. A plurality of sets of buffer memories divided into lower digits and having the same number of addresses TW as can be indicated by the lower digits, a bit indicating the validity of the contents of each address of the buffer memory, and a bit corresponding to the backup memory and the buffer memory. an index memory that displays the upper digits of the main memory with the same number of sets; and a register that indicates which set of the same address areas of the plurality of buffer memories should be loaded next with data in the main memory. , when another information processing device rewrites data in the main memory that is already held at a specific address in the buffer memory, the register changes to the corresponding address! A discrete 7-A memory control method characterized by specifying a buffer memory at a fixed address.