JPS6398749A - Data processor - Google Patents

Abstract

PURPOSE:To attain an access to a memory at a high speed by allocating an address area to which continuous accesses estimated to a special cache memory. CONSTITUTION:When it is previously known that the data stored in a certain area of an address space is used continuously or frequently like in the case of the table processing, etc., an instruction is put into a program to allocate the memory space of said area to a special cache SRAM 2. When this instruction is executed, a CPU produces a load request signal. Receiving this load request signal, a DMA transfer device 6 uses an interleaving system, for example, to store a large quantity of data in a certain area of a DRAM into the SRAM 2 at a high speed via data buses 7 and 8. An access is always given to a designated area via the SRAM 2 after the relevant instruction is carried out. Thus the cache hit rate is increased.

Description

[Detailed description of the invention] [Industrial application field] This invention especially has a cache memory.

The present invention relates to a data processing device.

[Traditional Karijutsu]

Figure 3 1 & 1 is a block diagram of the hardware required for the Direct Matsubuto Cache, which has the simplest configuration among conventional cache memories. In the figure, 1121 is the CPU (central processing unit), and the ring is the main memory (dynamic RAM is generally used. Hereinafter, D
Abbreviated as RAM. ) %11+ is a cache memory (generally a static RAM is used; hereinafter abbreviated as SRAM), which is composed of 13 tag RAMs and 8 data RAMs. (21 is a comparator that connects the tag (address upper pit) from the CPU and the tag (lii and t-Jtfl) commonly stored in the SRAM, and the space between is a cache control. In addition, l is the physical In the figure, the physical address is divided into eight fields: the Q4 tag field, and the bind index field. In data processing devices, cache SRAM...
It is divided into a data SRAM and a tag SRAM, the data SRAM containing the contents of the memory locations stored in the cache and receiving the addresses of the index fields. The tag SRAM receives the address of the index field (lυ and stores the tag field I corresponding to the upper address bits of DRAl13i.
When the paH) accesses this direct Matsubuto cache, the index field 051 is always used for the address of the tag SRAM, and the contents of the tag SRAM are compared with the CPU tag field. If there is a match, the cache contains the data for the accessed location in the data SRAM. This means "cache hit", and the read data is cached in the cache SRA.
M... is simply read out. If they do not match, it means a “cache miss” and the DRA
Execute M access money. Normally, upon a read cache miss, the DRAM data is not only returned to the CPU II, but also placed inside the cache SRAM.

In this way, the CPU and large memory (generally D R
A fast and relatively small memory (generally S
By arranging RAM), all the memory on a large scale is as if it were composed of high-speed SRAM,
Able to respond quickly.

[Problem that the invention seeks to solve]

In a cache system such as the one described above, for example, when accessing a large number of data in a certain area continuously,
If the data in that area is not stored in the cache SRAM IIIK, each time the data is accessed, the DR
AM access must be performed, which increases loss time when accessing the memory.

This invention was made to solve this problem, and it is known that a table in a certain area of address space is used continuously or frequently, for example, in table processing. A data processing device that can access memory quickly even when there is? The purpose is to obtain.

[Means for solving problems]

A data processing device according to the present invention is equipped with means for allocating a cache memory to an arbitrary area of a logical address space in a sock-air manner.

[Effect]

In this invention, memory access time is shortened by allocating address areas that are expected to be accessed continuously in the future, such as in table processing, to a special cache memory.

〔Example〕

FIG. 1 shows a block diagram showing an embodiment of the present invention, and . . . is a cache 8RAM composed of 8 tag RAMs and 8 data RAMs. (21 is a special cache SRAM consisting of data 8RAM that stores data and a tag register that stores data in Iii' of the tag.
+31 is a comparator that compares the tag on the address bus (upper pit of the address bus) and the tag on the cache SRAM 111; 141 is a comparator that compares the tag on the address bus with the tag on the special cache SRAM Ill; (6) is a DMA transfer device]6) (direct memory access transfer device) that can load a certain contiguous area in DRAM into a special cache SRAM at once, and 111+ is a direct memory access transfer device. Compared to the conventional one, load request signal t101, cache S RAM ill and special cache S R
Cache select signal + to select A M +21 and km
51 Added cache control text.

In the data processing device configured as above, C
The PU can access the cache S RAM Ill as usual. In addition, a special cache SRA is activated by the cache select signal (6)
MIll can also be accessed as before. However, the tag is not updated. For example, if it is known in advance that data in a certain area of the address space will be processed continuously or frequently, such as in table processing, the memory space of this area is stored in a special cache during the program. Insert a command to cut down on S RAM +21. When this instruction is executed, CPtr issues a load request signal, and the DMA transfer device (
6) For example, using an interleaving scheme, the data bus +71 t8) t' can be connected to
A large amount of data in a certain area in DRAM is stored in A M +21 at high speed.

After this instruction is executed, the cache memory is always accessed to the specified area, so the cache hit rate becomes high.

〔Effect of the invention〕

As explained above, this invention provides a special cache memory, makes the area of data stored in the cache memory contiguous, and specifies the area using a software square, so that the special cache memory can be freely stored in five memories. can be assigned within. Therefore, if it is known in advance that data in a certain area of the address space will be used continuously or infrequently, as in table processing, the access time during data processing can be shortened. can do.

[Brief explanation of the drawing]

FIG. 1 shows a block diadarum showing an embodiment of the present invention, FIG. 2+&l shows a block diadarum showing a conventional data processing device, and FIG. is cache S RAM, +
21 is a special cache memory. Note that the same reference numerals in Figure 6 indicate the same casings or corresponding parts.

Claims (2)

[Claims] (1) a main memory, at least one cache memory, at least one special cache memory, means for fixing an arbitrary address area of the main memory to an arbitrary address area of the special cache memory; A data processing device characterized by comprising: an instruction for executing the means. (2) The data processing device according to claim 1, further comprising means for unfixing the special cache memory and an instruction for executing the unfixing means.