JP3262182B2 - Cache memory system and microprocessor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory system, and more particularly to a cache memory system in which a plurality of direct-mapped cache memories are hierarchically connected and a microprocessor device.

[0002]

2. Description of the Related Art Recent advances in semiconductor devices show that the clock frequency of a microprocessor is improving year by year, but the access time of a DRAM or ROM as a main memory is not so short. In order to fill the speed gap, a method of providing a cache memory device composed of a high-speed and small-capacity memory between the processor and the main memory is often adopted.

The basic method of the cache memory is described in detail in Reference 1 described later. The main memory is divided into blocks of a predetermined capacity (usually about 16 bytes), and some of these blocks are stored in the cache memory. A block in the cache memory is called an entry.

Each entry in the cache memory is composed of three parts. (1) a data section for storing data; (2) a tag section for storing information (called a tag) indicating at which address a block is written;
(3) A status flag indicating whether or not valid data is stored in the entry. Depending on the method, the status may have a different meaning.

There are three types of cache memory configurations: a direct map system, a set associative system, and a full associative system.

[0006] The direct map system has one set of a tag section, a status flag, and a data section each constituted by a RAM. Lower bits of the address (index)
Is used as an address to access the RAM (tag section and data section). If the output from the tag section is equal to the upper bit (tag) of the address and the content of the status flag is "valid", the data section of that entry is valid (hit).

[0007] Set associative method Direct map type RAM is set to N sets (usually 2 or 4).
Pairs) and have access in parallel. If there is at least one hit set, the output of the data part of the hit set is selected.

Full associative system Each entry has a comparator in the tag section, and directly compares the address and the contents of the tag section. Normally, CAM (Content
Addressable Ram).

The hit ratios (the number of hits / the number of accesses) of the above three methods are higher in the order of <<. However, the access time of the cache memory also increases in the order of <<. The area of the LSI becomes larger in the order of <<. In particular, the system has many drawbacks, such as a large increase in area and complicated processing when no hit is made (when a miss is made).

[0010] Recent RISC (Reduced Ins)
fraction set computer) CPU
In this case, since the access time of the cache memory directly affects the clock frequency, the (direct map method) is often used.

FIG. 8 (based on the data of FIGS. 8 and 12 of Reference 1) shows the difference in the miss rate (1-hit rate) of the system. In the above method or the above, a miss (referred to as a conflict miss) occurs because different addresses are forced to use the same entry, so that the miss rate is higher than the method.

Another thing that can be read from FIG. 8 is that the cost / performance decreases as the capacity of the cache memory increases. As the cache capacity doubles, the miss rate decreases at a constant rate (0.7 to 0.8 times). On the other hand, the area when the cache memory is formed into an LSI is almost proportional to the capacity.

Therefore, one cache memory and one CPU are used.
In order to implement a chip LSI, a cache memory system with a small area and a low miss rate is desired.

Another conventional example will be described. An efficient cache memory method that adds a small, fully associative (method: low speed but low miss) cache memory to a direct map (high speed but high miss rate) cache memory is described below. Proposed in reference 2.

If the direct mapped cache (primary cache) misses, it accesses a full associative cache (they call it a victim cache) as a secondary cache.

When the secondary cache misses, the main memory is accessed. Both cache memories are CP
Since it is incorporated in the same LSI chip as U, transfer between the primary cache and the secondary cache is performed at high speed (one clock cycle).

Since most of the conflict misses of the direct-map cache memory hit the secondary cache, the effect of reducing the miss rate as much as doubling the capacity of the primary cache is 2 to 4 entries. Obtained in the next cache.

In Reference Document 2, by controlling the contents of the primary cache and the secondary cache so that there is no duplication, the effect is improved with the secondary cache having a small number of entries.

A disadvantage of this method is that a full associative method is used for the secondary cache. The full associative method has a remarkable increase in area because each entry has a comparator. Also, a control logic for determining which entry is replaced when a mistake is made (usually LRU: Leas)
t Recent Used) is complicated and the test is difficult. However, only the disadvantage of low speed is not a problem because it is used only when the primary cache misses.

Reference 1: "Computer Arc"
htake: A Quantitative
Applach, "John L. Hennesse
y & David A. Patterson, 1
990, Morgan Kaufmann Publ
ishers Inc.

Reference 2: "Improving Di"
Rect-Mapped Cache Perform
ance by the Addition of a
Small Fully-Associative
Cache and PrefetchBuffer
s "Norman P.S. Jooppi, 1990,
IEEE International Sympos
ium on ComputerArchtectur
e.

[0022]

The drawbacks of the above three conventional cache memory systems are summarized below. The direct map method is fast but has a high error rate. The area is also small. The set associative method is inferior in speed and area, and inferior in miss rate. The error rate is the lowest in the fully associative method. However, the speed is slow and the area is significantly large. The control logic is complicated and the test is difficult.

Another victim cache system utilizes the high speed of the direct map system,
This is an excellent system that achieves the low miss rate of the full associative system. However, since the method has drawbacks such as area and complexity, there is room for improvement.

An object of the present invention is to provide a cache memory system which occupies a small area and has a high performance when a CPU and a cache memory are integrated into an LSI, and a microprocessor device using this cache memory system. To provide.

[0025]

To achieve the above object, according to an aspect of the cache memory system according to the present invention, there is provided a cache memory system having a first cache memory and a second cache memory, the first cache memory
Applicable block specified by address to access means
Has a holding means for holding, each cache memory, a data memory, a tag memory, comprising a comparator, a hit generation circuit, data memory is for storing data in block units , The tag memory stores information (tag) indicating where the data stored in each block of the data memory is located in the address space, and the comparator stores the address tag in the address. And a hit generation circuit for generating a hit signal based on the content of the comparator, and the first cache memory for internal read access. Access means, and if no hit signal is generated in said first cache memory means, the corresponding block addressed by said reading is accessed.
The content of the lock is held in the holding means and the second
And if a hit signal is generated in the second cache memory means, the second cache memory means is accessed .
The contents of the corresponding block of the cache memory means are stored in the first
Write to the corresponding block of the cache memory means of the previous
The contents held in the storage means are stored in the second cache memo.
By writing to the corresponding block of the storage means, both corresponding blocks
Are exchanged, and if no hit signal is generated in the second cache memory means, an external memory is accessed.

Also, in an access due to a miss in the first cache memory means, an exclusive OR of a part of the address is taken to be the addresses of the tag memory and the data memory of the second cache memory means. It is.

Further, the memory capacity of the second cache memory means is smaller than the memory capacity of the first cache memory means.

Also, in the microprocessor device according to the present invention, when the first cache memory means accesses due to a miss, the exclusive OR of a part of the address is taken and the tag memory of the second cache memory means and the data are read. First with a cache memory system as the address of the storage memory
And the second cache memory means and the central processing unit are integrated on the same LSI chip, and transfer between the first cache memory means and the second cache memory means is performed every clock cycle.

Further, the microprocessor device according to the present invention is characterized in that the first and second cache memory means having a cache memory system in which the second cache memory means has a memory capacity smaller than that of the first cache memory means and the central processing unit. The device is integrated on the same LSI chip, and transfer between the first cache memory means and the second cache memory means is performed every clock cycle.

[0030]

In the conventional victim cache memory system described above, a high-speed and low miss rate cache system is constructed using a primary cache memory of a direct map system and a small-scale secondary cache memory of a full associative system.

On the other hand, the present invention uses a direct-mapped primary cache memory and a small-scale direct-mapped secondary cache memory to configure a cache system that is fast, has a low miss rate, and is easy to control. It has an original content.

[0032]

Next, an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram showing Embodiment 1 of the present invention.

In FIG. 1, 100 is a microprocessor LSI, 110 is a CPU (central processing unit), 120 is a primary cache memory, 140 is a secondary cache memory, and 160 is a main memory (main storage device). Here, the CPU 110, the primary cache memory 120, and the secondary cache memory 140 are connected to the same microprocessor L.
The microprocessor is integrated with the SI 100 to constitute a microprocessor device.

Reference numeral 111 designates a memory address in byte units and the size of data to be accessed.
, An address bus 112, a data bus input / output by the CPU 110, and a primary cache memory 113.
A bus wait signal 0 is output, and 131 is an address bus output from the primary cache memory 120.

Reference numeral 132 denotes the primary cache memory 12
0 is a data bus for input / output, and 136 is a main memory 16
0 is a bypass for transmitting data of 0 to the primary cache memory 120, 133 is a bus waiting signal output from the secondary cache memory 140, 151 is the secondary cache memory 14
0 is an address bus output, 152 is a data bus input / output by the secondary cache memory 140, and 153 is a bus waiting signal output by the main memory 160.

The addresses 121 and 141 are addresses 111 and 131.
Lower bits (index) 2 ⁱ words × t bits of the tag memory for storing the high-order bits of the address 111, 131 (tag) as the address, 122 and 142 as an address the lower bits of the address 111, 131 (index) of This is a status flag memory of 2 ⁱ words × 2 bits indicating whether each entry is valid.

123 and 143 are addresses 111 and 131
Data buses 112 and 132 or data bus 13 using lower bits (index and offset) of
2, ^{(1 + b-2)} words × 32-bit data memory for reading and writing the value of 2,152, and 124 and 144 are addresses 11
1,131 upper bits (tags) and tag memory 12
This is a comparator for detecting whether or not the outputs 1 and 141 match.

125 and 145 are comparators 124 and 144,
From the outputs of the status flag memories 122 and 142 and the addresses 111 and 131, the cache memories 120 and 14 are read.
0 is a control circuit.

Reference numerals 126 and 146 denote the cache memory 12
An address buffer 134 generates a memory address when 0 and 140 are missed. A tag buffer 134 temporarily holds the tag information of the tag memory 121 and transmits the tag information to the tag memory 141.

Reference numeral 135 denotes a tag buffer for temporarily storing data in the data memory 123 and transmitting the data to the data memory 143.

FIG. 2 shows how the address values of the address buses 111 and 131 are used in the cache memories 120 and 140. If the block size is 2 ^b bytes, the offset in the block is b bits wide, and if the number of cache entries is 2 ⁱ entries, the index has an i bit width, and the tag has a width obtained by subtracting the index and offset from the bit width of the address. .

For example, if the primary cache capacity is 8 Kbytes and the block size is 16 bytes at a 32-bit address, the offset in the block is 4 bits (2 ⁴ = 1).
6) Since the number of entries is 512 (= 8K / 16), the index is 9 bits (2 ⁹ = 512) and the tag is 1
This is 9 bits (= 32-9-4).

The block size b is the same for the primary cache memory 120 and the secondary cache memory 140.

Next, the operation of the cache memory system shown in FIG. 1 will be described with reference to FIGS.

The operation of the primary cache memory 120 controlled by the control circuit 125 is shown in FIG. It is assumed that the content of the status flag 122 has been initialized to "invalid".

When a memory access by the CPU 110 occurs, the memories 121 and 122 are read using the index of the address 111 as an address (step 301).
The comparator 124 compares the output of the tag memory 121 with the tag of the address 110 (step 302). If the comparisons are equal and the status flag 122 indicates "valid" or "write", it is a hit, otherwise it is a miss.

If a hit occurs, the contents of the data memory 123 are read / written via the data bus 112 using the index of the address 111 and the offset in the block as addresses (steps 304 and 305).

When the access from the CPU 110 is a write, the contents of the data memory 123 are stored in the specified size (byte width,
(Word width, etc.), and write "write" into the status flag (steps 305, 306).

If a mistake is made, first, the status flag 1
It is determined whether 22 is "write", "valid" or "invalid" (step 307). If "write", the entry specified by the index is written to the secondary cache memory 140 (step 308). At this time, the value read from the tag memory 122 is used as an address, and the data is the contents of the data memory 123. If the status flag 122 is "valid", the tag and data of the corresponding entry are stored in the buffers 134 and 135 (step 309).

When the access from the CPU 110 is a read operation, an entry specified by the address 111 is read from the outside. For the read entry, the data memory 1 has the size specified by the address 111.
23 is transferred to the CPU 110 via the data bus 112 (step 311). At the same time, tag memory 1
21 and the status flag 12
"Valid" is written in 2 (steps 312 and 313).

If the access from the CPU 110 is write, the tag at the address 111 is written to the tag memory (step 314). At the same time, the data memory 123
Is rewritten only in the portion of the designated size (byte width, word width, etc.) at the designated address in the entry, and "write" is written in the status flag (step 3).
05, 306).

FIG. 4 shows the operation of the secondary cache memory 140 controlled by the control circuit 145. The operation is
Similar to the primary cache memory 120 but partially different.

When a memory access by the primary cache memory 120 occurs, the memories 141 and 142 are read using the index of the address 131 as an address (step 401), and the output of the tag memory 141 and the address 1 are read.
The 31 tags are compared by the comparator 144 (step 40).
2). If the comparisons are equal and the status flag 142 indicates "valid" or "write", it is a hit, otherwise it is a miss.

When a hit occurs, the contents of the data memory 143 are read / written via the data bus 132 using the index of the address 131 and the offset in the block as addresses (steps 404 and 408). When the access from the primary cache memory 120 is read, the contents of the corresponding entry of the primary cache memory stored in the buffers 134 and 135 are stored in the memories 141 and 1.
43 (steps 405 and 406).

Then, the status flag 142 is written with the status value of the corresponding entry in the primary cache memory for a read access, and "write" for a write access (steps 407 and 409).

When a mistake is made, first, the status flag 1
It is determined whether 42 is "write", "valid" or "invalid" (step 407). If "write", the entry specified by the index is written to the main memory 160 (step 411).

At this time, the value read from the tag memory 142 is used as an address, and the data is the contents of the data memory 143. Access to the outside is for one entry, and when the block size is larger than the bus width, a plurality of bus cycles are required.

If the access from the primary cache memory 120 is a read, the entry specified by the address 131 is read from the main memory, and is passed through the secondary cache memory (152, 136, 132). The data is transferred to the primary cache memory 120.

If the access from the primary cache memory 120 is a write, then the tag of the address 131 is written into the tag memory 141 (step 414). At the same time, the contents of the data memory 143 are rewritten only in the portion of the specified size (byte width, word width, etc.) at the specified address in the entry, and "write" is written in the status flag (step 408, 409).

Until the processing when the primary cache memory 120 misses is completed, the control circuit 125 outputs the signal 113
CPU 110 is kept waiting. Similarly, access to the secondary cache memory 140 (step 408,
410) may be delayed by the control signal 133.

The control method of the cache memory alone is known.

The control method of the cache memory alone described here is generally a method called write-back (also called copy-back or store-in). Status flag 1
22 and 142 have three states ("invalid", "valid", and "write"). Write accesses from the upper level are not directly transmitted to the lower level.

When there is a write access from the upper level, the lower level memory is written directly (called a write-through method).
There is also. The status flags 122 and 142 have only two states ("invalid" and "valid"), and the control is simple.
However, the miss rate is higher than the write-back method.

There is also a write-back method in which the number of status flags is further increased in order to support a microprocessor.

The difference from the normal write-back method is that
This is to prevent data duplication between the secondary cache memory and the secondary cache memory.

In a read access, if both the primary and secondary cache memories are missed, the main memory
When data is transferred to the secondary cache memory and the primary cache memory misses and the secondary cache memory hits, the data in the primary cache memory and the secondary cache memory are exchanged. By controlling in this manner, data at the same address does not overlap in the primary cache memory and the secondary cache memory. Therefore, the efficiency of the secondary cache memory is increased.

The gist of the present invention is that the hierarchical structure and the primary / secondary cache memory can be accessed in the same access time, not the control method of the cache memory alone, and the transfer between the primary and secondary cache memories. Can be done at high speed.

It goes without saying that any combination of these control methods for the cache memories implemented in the cache memories 120 and 140 is in accordance with the gist of the present invention.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described. FIG. 5 shows a second embodiment of the present invention. There are two differences from the first embodiment (FIG. 1). One is that in the secondary cache memory 140, the memories 141, 142, 1
That is, the index serving as the address 43 is generated using the index generation circuit 146. The other is that the width (t bits) of the tag memory is wider than in the first embodiment.

FIGS. 6 and 7 show how the address value of address bus 131 is used in cache memory 140.
Shown in Unlike FIG. 2, the tag is obtained by subtracting the intra-block offset from the address. The index is
A part of the tag is obtained by hashing by the index generation circuit 146. As the hash function, a function obtained by taking an exclusive OR in a hierarchical manner as shown in FIGS. 6 and 7 is used.

It is preferable that the hashed portion of the address includes the index of the primary cache memory and a part of the tag (at the bit position of the address). This is because conflict errors are eliminated and the error rate is reduced.

In the example of FIG. 6, the bits to be hashed are packed from the bottom, but may be obtained from the entire tag as shown in FIG.

In FIGS. 6 and 7, the exclusive OR has a two-stage tree structure. However, it goes without saying that the exclusive OR may be a tree having only one stage or a tree having three or more stages.

The access time of the secondary cache memory 140 is extended by the index generation circuit 146. However, by operating the index generation circuit 146 in parallel with the access from the CPU 110 to the primary cache memory 120, the access time can be prevented from being lengthened.

Here, the performance and hardware cost of the conventional example and the embodiment will be calculated.

The relative performance of the CPU, where the performance when a no-wait memory can be accessed every clock is 1.0, can be expressed as follows. It is assumed that a memory access is generated from the CPU every clock.

Relative performance = 1 / average access time (1) where: M1 miss rate of primary cache memory M2 miss rate of secondary cache memory B1 access time of primary cache memory (clock)
k) B2 Secondary cache memory access time (clock)
k) B3 Main memory access time (clock) b Block size (Byte) a Bus width (Byte)

When the cache memory has one layer (conventional system), relative performance = 1 / {(1−M1) × B1 + (M1 × b / a × B3)} (2)

When the cache memory has two levels (victim cache or the present invention), relative performance = 1 / ｛(1-M1) + (M1 × (1-M2) × b / a × B2) + (M1 × M2) × b / a × B3)｝ (3)

Here, an example will be given. B1 = 1 clock, B2 = 1 clock, B3 = 8 clock b = 16 Byte, a = 4 Byte (4)

An application (diff: 16K)
Table 1 shows the results of measuring the capacity and the miss rate of the cache memory of the direct map system for data of about B). The relative performance was determined from equations (2) and (4).

[0083]

[Table 1]

Table 2 shows the measurement results of the victim cache system and Examples 1 and 2 using the same application. The relative performance was determined from equations (3) and (4).
All primary cache memories are of the 8K byte direct map system (same as Example 1 in Table 1).

Example 3 is an example of a victim cache, Examples 4 and 5 are examples of the first embodiment of the present invention, and Examples 6 and 7 are examples of the second embodiment of the present invention.

FIG. 8 summarizes the performances of the above six examples. Further, FIG. 8 shows the relative area (Example 2 was set to 1) and the efficiency (relative performance / relative area) when each example was formed into an LSI.

[0087]

[Table 2]

[0088]

As described above, the cache memory system according to the present invention has the following effects. High performance. As can be seen from FIG. 8, the performance of the present invention is high. In the second embodiment (Example 7), the performance is higher than in Example 2 (in which the capacity of the primary cache memory is doubled). Good hardware efficiency. As can be seen from FIG. 8, the amount of hardware according to the present invention (area when implemented in LSI)
Are smaller than those in Example 2 (in which the capacity of the primary cache memory is doubled). In Example 6 (Example 2), the same efficiency is realized with a smaller area than the victim cache (Example 3). In Example 3, since the fully associative method is used, the area efficiency is very poor. Example 7 achieves higher performance than Example 2 (a 16 Kbyte primary cache memory) simply by adding a 2 Kbyte secondary cache memory to an 8 Kbyte primary cache memory. Hardware is simple. As shown in the conventional example,
The full associative scheme used in the secondary cache memory of the victim cache scheme has a disadvantage that the control logic is complicated. A control logic (usually LRU: Le) that determines which entry is replaced when a mistake is made
The “ast Recent Used” is complicated, and usually accesses the data memory via a comparator, but must be able to perform random access at the time of replacement. Therefore, testing is also difficult.

However, the secondary cache memory according to the present invention employs a direct map system and is very simple. The hardware is as simple as SRAM + one comparator. In addition, since the primary cache memory and the secondary cache memory are of the same type, the control circuit can be easily designed (reusable).

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a hardware configuration according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an address in a direct map system.

FIG. 3 is a diagram illustrating the operation of the present invention.

FIG. 4 is a diagram illustrating the operation of the present invention.

FIG. 5 is a diagram illustrating a hardware configuration according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating a configuration of an address according to a second embodiment.

FIG. 7 is a diagram illustrating a configuration of an address according to a second embodiment.

FIG. 8 is a diagram showing a miss rate of the conventional cache memory system.

FIG. 9 is a diagram showing the effect of the present invention.

[Explanation of symbols]

 Reference Signs List 100 microprocessor LSI 110 CPU 120 primary cache memory 140 secondary cache memory 160 main memory 121, 141 tag memory 122, 142 status flag memory 123, 143 data memory 124, 144 comparator 125, 145 control circuit 146 index Generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI G06F 12/08 509 G06F 12/08 509D 597 597 (56) References JP-A-4-49445 (JP, A) JP-A Sho58 JP-A-91573 (JP, A) JP-A-61-241853 (JP, A) JP-A-53-33023 (JP, A) JP-A-61-15247 (JP, A) JP-A-54-89531 (JP, A) )

Claims (5)

(57) [Claims] 1. A cache memory system having a first cache memory and a second cache memory,
At an address to access the first cache memory means
Has a holding means for holding the block to be specified, each cache memory, a data memory, a tag memory, a comparator, and a hit generation circuit, data memory, the data in block units The tag memory stores information (tag) indicating where the data stored in each block of the data memory is located in the address space, and the comparator includes:
An address tag in an address is compared with the output of the tag memory.The hit generating circuit generates a hit signal based on the content of the comparator, and the hit signal is generated for an internal read access. Accessing the first cache memory means, and if no hit signal is generated in the first cache memory means, the address is read by the read.
The contents of the corresponding block designated as address
Appropriate bromide of the second accesses the cache memory means, said second of said if a hit signal is generated in the cache memory means second cache memory means while lifting
The contents of the corresponding block of the first cache memory means.
Write to the lock and store the content held in the
Write to the corresponding block of the second cache memory means
The contents of both corresponding blocks are exchanged, and an external memory is accessed unless a hit signal is generated in the second cache memory means. 2. The method according to claim 2, wherein, when the first cache memory is accessed due to a miss, an exclusive OR of a part of the address is calculated to obtain the address of the tag memory and the address of the data memory of the second cache memory. The cache memory system according to claim 1, wherein: 3. The cache memory system according to claim 2, wherein a memory capacity of said second cache memory means is smaller than a memory capacity of said first cache memory means. 4. The first and second cache memory units having the cache memory system according to claim 2 and a central processing unit are integrated on the same LSI chip, and the first cache memory unit and the second cache memory unit are integrated. Wherein the transfer between the cache memory means is performed every clock cycle. 5. The first and second cache memory units having the cache memory system according to claim 3 and a central processing unit are integrated on the same LSI chip, and the first cache memory unit and the second cache memory unit are integrated. Wherein the transfer between the cache memory means is performed every clock cycle.