JPH06124237A - Address translation buffer device - Google Patents

Abstract

PURPOSE:To improve the efficiency of an entire computer system by dynamically changing the ratio of a high speed Translation Lookaside Buffer mechanism (TLB) replacement inhibited area and a replacable area by the hit ratio of the TLB in the replacement control of the TLB. CONSTITUTION:The entire area of the TLB is divided into a first entry replacement inhibited area and a first entry replacable area and further, the first entry replacable area is divided into a second entry replacement inhibited area and a second entry replacable area. The boundary of the second entry replacement inhibited area and the second entry replacable area is changed by the hit ratio of the TLB and the ratio of the TLB replacement inhibited area and the replacable area is dynamically changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address translation buffer device having a translation lookaside buffer mechanism called TLB for executing high speed translation of virtual addresses and real addresses in a page virtual memory computer system.

[0002]

2. Description of the Related Art In a virtual memory system, a central processing unit (Central Processing Unit),
A virtual address (Virtual Address, hereinafter referred to as VA) output from a CPU (hereinafter referred to as CPU) is a memory management device (Mem) connected to the CPU.
ory Management Unit (hereinafter referred to as MMU), a physical address (Physical Address) in the real memory, hereinafter referred to as PA.
Used to access the real memory.

Since the MMU translates the virtual address VA into the physical address PA, the virtual address VA
An address conversion table in which a pair of a physical address PA and a physical address PA is used as one entry item is used. Since the address translation table is generally large, all the tables are arranged in the memory, and a part of the table is placed in the address translation buffer or the translation look-aside buffer (Translation Look-aside) in the MMU.
e Buffer, hereinafter referred to as TLB), is stored in a cache memory to speed up conversion.

If the virtual address VA output from the CPU matches with any entry in the TLB (hereinafter referred to as a TLB hit), the physical address PA is immediately obtained and the system can obtain high efficiency. I can, but
If it does not match any of the entries in the TLB (hereinafter referred to as TLB miss), the MMU must search the address translation table in the memory, which reduces the efficiency of the system.

In order to realize a system with high address conversion efficiency in MMU, it is necessary to hit TLB with high probability.

[0006] One factor that determines the TLB hit rate is
An entry replacement method is important, such as how to perform entry replacement when a TLB miss occurs. There are two typical methods, one is L which replaces the entry with the least reference frequency at the time when an entry error occurs and a new entry.
The RU (Least Recently Used) method, and the other is a random method that randomly determines an entry to be replaced. The LRU method can obtain a higher hit rate than the random method, but since the control is complicated, the circuit scale increases in proportion to the number of TLBs.
When mounting with an LSI, a random method is often adopted.

By the way, a plurality of address spaces of a computer system are usually prepared, and at least an area accessed by the operating system in the supervisor mode and an area accessed by the user program in the user mode are distinguished from each other. In a system having a plurality of address spaces such as a user area and a supervisor area, the CPU uses an address space identifier (Address Space Id) to identify these address spaces.
The address space is divided by outputting an "entifier" (hereinafter, ASI) signal together with the address signal. A CPU having an ASI signal has a load / store instruction that specifies ASI as one operand.

As a method for obtaining a high hit rate of the TLB in a system in which the replacement method is a random method, a so-called entry lock control method in which an entry that is surely frequently accessed is excluded from the entry replacement targets is well known. ing. This method will be described with reference to FIG. 6 is 1
It is a TLB of 28 entries. Entries 0 to 2 are entry replacement prohibited areas where entry replacement is prohibited,
Entries other than the entries 0 to 2 are entry replaceable areas in which entries can be replaced. The entry replaceable area can identify the beginning of the area by the entry replacement initial register, and the entry replacement register randomly changes the value within the range of the entry replaceable area, and selects the entry to be replaced when the TLB miss occurs. Shows. Since an entry in a so-called supervisor area such as an interrupt vector or interrupt routine of the operating system is frequently accessed, a high TLB hit rate can be obtained by arranging the entry in the entry replacement prohibited area. Since the entry replacement initial register can be written in the supervisor mode, it is possible to change the sizes of the entry replacement prohibited area and the entry replacement enabled area.

[0009]

[Problems to be Solved by the Invention]
The LB device improves the TLB hit rate by performing the TLB entry lock control as described above. Normally, at the time of system initialization, only static control such as writing to the entry replacement initial register and fixing the entry replacement prohibited area is performed.
Since it is necessary to reset the entry replacement initial register in order to perform dynamic control, it is very difficult to cope with a change in the TLB hit rate that greatly changes depending on the program to be executed.

Therefore, in the present invention, in the TLB replacement control, the ratio of the TLB replacement prohibited area to the replaceable area is dynamically changed according to the hit rate of the TLB to improve the efficiency of the entire computer system. An object is to provide a buffer device.

[0011]

In order to achieve the above-mentioned object, the present invention uses a translation lookaside buffer as a part of an address translation table configured with a pair of a virtual address and a physical address as one entry. An address translation buffer device used in a virtual storage computer system for performing a translation from a virtual address to a physical address, the translation lookaside buffer area including a first entry replacement prohibited area and a first entry replacement prohibited area. First entry initial replacement register means for holding an entry number to be divided into an entry replaceable area, and first entry replacement register means for holding an entry number of one of the first entry replaceable areas,
One of the second entry replacement possible register means for holding an entry number for dividing the first entry replacement possible area into a second entry replacement prohibited area and a second entry replacement possible area; Second entry replacement register means for holding an entry number and a translation lookaside register when the translation lookaside buffer is accessed.
A translation lookaside buffer hit ratio detecting means for detecting a hit ratio of the buffer; and a second entry replacement initial register means for detecting the hit ratio detected by the translation lookaside buffer hit ratio detecting means. The present invention is characterized by further comprising entry replacement control means for changing a value and automatically changing a ratio of the second entry replacement prohibited area and the second entry replaceable area.

[0012]

First, the principle of the present invention will be described with reference to FIGS.

In the present invention, the entire area of the TBL (translation lookaside buffer) is
The first entry replaceable area and the first entry replaceable area are divided, and the first entry replaceable area is further divided into the second entry replace prohibited area and the second entry replaceable area.

In FIG. 1, the first entry replacement initial register means sets the TLB as a first entry replaceable area and a first entry replaceable area.
Conventionally, an entry number for dividing the entry replacement prohibited area into two areas is held, and in addition to this, one entry number in the first entry replaceable area is designated by the first entry replacement register means. It becomes possible to perform the TLB control similar to that of FIG. 6 described in the technology. The second entry replacement initial register means holds an entry number for dividing the first entry replaceable area into two areas, a second entry replaceable area and a second entry replace prohibited area.

When a TLB miss occurs in the supervisor mode, one entry in the entry replaceable area indicated by the first entry replacement register is replaced as shown in FIG. When a TLB miss occurs in the TLB in the user mode, as shown in FIG. 3, one entry in the entry replaceable area indicated by the second entry replacement register is replaced. As a result, the second entry replacement prohibited area that is replaced only in the supervisor mode is obtained.

Next, the operation of the present invention will be described with reference to the schematic block diagram shown in FIG. At the time of system initialization, each register means 1, 2, 3, 4 is set to an appropriate value. Further, it is assumed that the TLB hit rate detection means 6 is also initialized at the time of system initialization, and the TLB access count number for detecting the hit number and the target TLB hit number are set in the internal register. Virtual address VA input to TLB7
Are compared in the TLB, and if the TLB is hit, the TLB
At the same time as outputting the TLB hit signal to the hit ratio detecting means 6, the physical address PA is output. When a TLB miss occurs, the TLB 7 sends the TLB hit rate detection means 6 to the TL.
At the same time as outputting the B-miss signal, the TLB replacement control means 5 is requested to replace the TLB entry. The TLB replacement control means 5 determines from the ASI signal whether the TLB access causing the TLB miss is the user mode or the supervisor mode, and the first entry replacement initial register 1 and the first entry replacement are determined according to the determination result. A combination of the registers 2 or the second entry replacement initial register 3 and the first
Either the combination of the entry replacement registers 4 is selected, and replacement control between the new entry input from the data bus and the TLB entry indicated in the entry replacement register is performed. When the TLB access in the supervisor mode reaches the TLB access count number, the TLB hit rate detecting means 6 compares the value of the internal counter with the target TLB hit number. If the value of the internal counter has not reached the target number of hits, the TLB replacement control means 5
A request to add the value of the second entry replacement initial register is issued to. In addition, the TLB access in the user mode is the above T
When the LB access count number is reached, the value of the internal counter is compared with the target TLB hit number. If the value of the internal counter has not reached the target number of hits, T
A request for subtracting the value of the second entry replacement initial register is issued to the LB replacement control means 5. However, the second entry replacement initial register limits the value of the first entry replacement initial register.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The features of the present invention will be specifically described below based on embodiments with reference to the drawings.

Here, an address translation buffer device used in the page virtual memory computer system, which is a part of an address translation table constructed by a pair of a virtual address and a physical address as one entry,
An address translation buffer device, which is held in a TLB, which is a high-speed cache memory configured by the full associative method, and translates a virtual address to a physical address will be described as an example.

FIG. 5 is a block diagram showing an embodiment of the address translation buffer device of the present invention.

The first entry replacement initial register means 1 is
As shown in FIG. 2, this is a register for storing an entry that divides the TLB 7 into a first entry replacement prohibited area and a first entry replaceable area. In addition, the first entry replacement register means 2 uses the first entry replaceable area for the next TL.
This is a register for storing an entry to be replaced when a B miss occurs.

The second entry replacement initial register means 3 is
As shown in FIG. 3, this is a register for storing an entry that divides the first entry replaceable area into a second entry replacement prohibited area and a second entry replaceable area. The second entry replacement register means 4 is a register for storing an entry to be replaced when the next TLB miss occurs in the second entry replaceable area.

The TLB replacement control means 5 changes the first entry replacement register 2 and the second entry replacement register 4 and at the same time performs TLB replacement control and receives a register change request signal from the TLB hit ratio detection means 6. It is a control means for changing the second entry replacement initial register 3.

The TLB 7 constitutes an address translation buffer for storing a pair of a virtual address VA and a physical address PA as an entry. The TLB 7 compares the input virtual address VA with the entry, and checks the TLB hit, TL
The B miss is detected and each signal is output to the outside.

The TLB hit ratio detecting means 6 is a device for detecting the TLB hit ratio.

The details of the TLB hit rate detecting means 6 will be described below.

TLB hit count register means 101
Is T when changing the second entry replacement initial register 3.
It is a register means for storing the LB hit rate. The AND gate 102 receives the ASI signal, the output signal of the comparator 103, and the output signal of the comparator 109, and outputs a change signal for the second entry replacement initial register. The comparator 103 is
The output signals of the TLB hit count register means 101 and the multiplexer 104 are input and comparison is performed. The multiplexer 104 multiplexes the outputs of the user mode TLB hit count register (shown as u hit register in the figure) 105 and the supervisor mode TLB hit count register (shown as s hit register in the figure) 106 by the ASI signal. Is. User mode TLB hit count register 105
Is a counter device that counts TLB hits in user mode. The supervisor mode TLB hit count register 106 is set to T in the supervisor mode.
A counter device that counts LB hits. TLB
The hit counter means 107 is a counter device that counts TLB hits. The TLB access count register means 108 is a register device that stores the sampling number of TLB access for counting TLB hits. The comparator 109 is a device that receives the output signals of the TLB access count register means 108 and the multiplexer 110 as input and performs comparison. Multiplexer 110
Is a multiplexer device that multiplexes the outputs of the user mode access count register 111 and the supervisor mode access count register 112 by an ASI signal. The user mode access count register 111 is a counter device that counts TLB accesses in the user mode. The supervisor mode access count register 112 is a counter device that counts TLB accesses in the supervisor mode. The TLB access counter means 113 is a counter device that counts TLB accesses.

Next, the operation of the embodiment shown in FIG. 5 will be described.

When the virtual address VA input to TLB7 matches an entry inside TLB7, TLB7 returns T
The LB hit signal is output, and the physical address PA corresponding to the virtual address VA is output. TL if not matched
B7 outputs a TLB miss signal, and TLB replacement control means 5
Replaces the entry pointed to by the new entry entered from the data bus. TLB replacement control means 5
Recognizes the access mode when the TLB miss occurs by the ASI signal, and makes the entry to replace the contents of the second entry replacement register means 4 in the case of user mode access, and the first entry replacement register means 2 in the case of supervisor mode access. As an entry that replaces the contents of
Instruct TLB7. Replacement control between a new entry input from the data bus and the TLB entry indicated in the entry replacement register is performed. TLB output by TLB7
The hit and TLB miss signals are also input to the TLB hit counter means 107 and the TLB access counter means 113. The TLB access counter means 113 identifies the access mode by the ASI signal, and in the case of the user mode, the user TLB access count register 111.
, Supervisor TL in supervisor mode
The B access count register 112 is selected as an input, the value of the register is incremented by +1 and stored again in each register. One of the values of the user TLB access count register 111 and the supervisor TLB access count register 112 is selected by the ASI signal and the multiplexer 110, and the comparator 109 selects TLB.
Compared with access count register means 108, TL
1 if equal to B access count register means 108
Is output. User TLB access count register 1
11 and supervisor TLB access count register 112 are again set to 0 by this signal.

The TLB hit counter means 107 uses ASI.
The mode of access is identified by a signal, and in the case of the user mode, the user TLB hit count register 105
, Supervisor TL in supervisor mode
The B hit count register 106 is selected as an input, the register value is incremented by +1 and stored again in each register. One of the values of the user TLB hit count register 105 and the supervisor TLB hit count register 106 is selected by the ASI signal and the multiplexer 104, the comparator 103 compares the selected value with the TLB hit count register means 101, and the TLB hit count register means 101. If smaller, 1 is output. The user TLB hit count register 105 and the supervisor TLB hit count register 106 are
It is set to 0 again by this signal.

The AND gate 102 to which the comparator 103, the comparator 109, and the ASI signal are input outputs the change request signal of the second entry replacement initial register means 3 when the comparator 103 outputs 1 and the comparator 109 outputs 1. It is given to the TLB replacement control means 5. The TLB replacement control means 5 receives the change request signal and A
The access mode is identified by the SI signal, and the second entry replacement initial register means 3 is incremented by +1 in the supervisor mode, and the second entry replacement initial register means 3 is decremented by -1 in the user mode. However, the value of the second entry replacement initial register means 3 is controlled by the TLB replacement control means 5 so that the first entry replacement initial register means 1 has a lower limit and does not take a value less than that.

The configuration and operation of the above-described address translation buffer device of the present invention can be summarized as follows.

In the present invention, the area of the TLB 7 in which the entries are consecutively ordered is composed of a first entry replacement prohibited area where replacement is prohibited except for an explicit replacement by the program, and an area other than the first entry replacement prohibited area. Therefore, not only the explicit replacement by the program but also the first entry that can be replaced when a TLB miss occurs is divided into two areas, the replaceable area and the first entry as a boundary of these two areas. The first entry number of the replaceable area is held in the first entry replacement initial register means 1 composed of a register accessible by the program. Also, one of the first entry replaceable areas
First entry replacement register means 2 composed of registers which can access one entry number from a program
To hold.

Further, the first entry replaceable area is
It is divided into two areas, a second entry replacement prohibited area in which replacement is prohibited during execution of a user program and a second entry replaceable area in which replacement is possible when a TLB miss occurs, and indicates the boundary between these two areas. As a result, the first entry number of the second entry replaceable area is held in the second entry replacement initial register means 3 composed of a register accessible from the program. Further, one entry number of the second entry replaceable area is held in the second entry replacement register means 4 which is a register accessible by the program.

Then, the TLB hit ratio detection means 6 counts the number of TLB hits with respect to a certain number of times of accessing the TLB in each of the supervisor mode and the user mode, and the TLB replacement control means 5 detects a TLB miss. , If the access source is a user program or user data, the entry having the number stored in the second entry replacement register 4 is replaced with a new entry, and if the access source is a supervisor program or supervisor data, the first entry replacement register The entry having the number stored in 2 is replaced with a new entry, and the value of the second entry replacement initial register means 3 is changed according to the result of the TLB hit ratio detection means 6 to automatically change the second entry. Entry replacement prohibited area and second entry replacement To change the ratio of Noh area.

[0035]

According to the present invention, in the TLB replacement control, the ratio of the TLB replacement prohibited area to the replaceable area is dynamically changed according to the TLB hit rate, so that the optimum TLB control is always performed. Enabled, TLB
It is possible to obtain an address translation buffer device which has a high hit rate and which improves the efficiency of the entire computer system.

[Brief description of drawings]

FIG. 1 is a block diagram of T in the address translation buffer device of the present invention.
It is a conceptual diagram showing the state of LB area division.

FIG. 2 is a conceptual diagram showing a state of TLB area division when a TLB miss occurs in the supervisor mode.

FIG. 3 is a conceptual diagram showing a state of TLB area division when a TLB miss occurs in the user mode.

FIG. 4 is a block diagram showing a basic configuration of an address translation buffer device of the present invention.

FIG. 5 is a block diagram showing an embodiment of an address translation buffer device of the present invention.

FIG. 6 is a conceptual diagram showing a state of TLB area division in the conventional technique.

[Explanation of symbols]

1 ... 1st entry replacement initial register means, 2 ... 1st entry replacement register means, 3 ... 2nd entry replacement initial register means, 4 ... 2nd entry replacement register means, 5 ... T
LB replacement control means, 6 ... TLB hit rate detection means, 7 ...
TLB, 101 ... TLB hit count register means,
102 ... AND gate, 103, 109 ... Comparator, 10
4, 110 ... Multiplexer, 105 ... User mode T
LB hit count register, 106 ... Supervisor mode TLB hit count register, 107 ... TLB
Hit counter means, 108 ... TLB access count register means, 111 ... User mode TLB access count register, 112 ... Supervisor mode TLB
Access count register, 113 ... TLB access counter means

Claims (1)

[Claims] 1. A virtual look-aside buffer that holds a part of an address translation table configured with a pair of a virtual address and a physical address as one entry and translates the virtual address to the physical address. An address translation buffer device used in a storage computer system, the first entry holding an entry number for dividing an area of the translation lookaside buffer into a first entry replacement prohibited area and a first entry replaceable area. Initial replacement register means, first entry replacement register means for holding one entry number of the first entry replaceable area, first entry replaceable area to second entry replacement prohibited area and second entry replacement The second that holds the entry number that divides the possible area Entry replacement initial register means, second entry replacement register means for holding an entry number of one of the second entry replaceable areas, and translation look when the translation lookaside buffer is accessed Translation lookaside buffer hit ratio detection means for detecting the hit ratio of the aside buffer, and the second entry replacement initial register according to the hit ratio detected by the translation lookaside buffer hit ratio detection means An address translation buffer device comprising: an entry replacement control means for changing the value of the means and automatically changing the ratio of the second entry replacement prohibited area and the second entry replaceable area.