JP2001282616A - Memory management system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the use efficiency of a memory resources without being conscious as whether the page size is smaller than a cache memory. SOLUTION: In a memory managing mechanism that is equipped with a main storage device and the cache memory and provided for a processor which refers to the main storage device by using a physical page address replacing an inputted virtual page address, a non-cacheable control part (11) uses a page size bit (PZ) stored in a page display entry (TLB) (1) and a non-cacheable bit (N) showing a value, specifying whether a page specified with the physical page address is registered in the cache memory and sets a value specifying nonregistration to a non-cacheable bit, when the page size bit shows a value indicating that the page size is smaller than set size (size of cache memory, block data size × the number entered).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a system LSI (Large) incorporating a cache memory and a general-purpose memory.
The present invention relates to a memory management method (memory management mechanism) for improving the use efficiency of a built-in general-purpose memory in Scale Integration.

[0002]

2. Description of the Related Art In recent years, with the remarkable progress of semiconductor process technology, it has become possible to manufacture a system LSI in which not only a processor core but also various memories are built in one LSI. These various memories include a cache memory, an RO
M (Read Only Memory), flash memory, general-purpose memory (SRAM (Static Ran)
dom Access Memory), DRAM (D
dynamic Random Access Memo
ry)). There is a possibility that a plurality of combinations are built in according to the respective applications.

Further, since a processor core can access these various memories at high speed, the capacity to be built in is also increasing gradually. In recent years, even in embedded processors, a general-purpose operating system (OS) is operated to improve program development efficiency.

For this reason, even in a processor for embedded use, a memory management mechanism (MMU: Memory Manager) is used.
ment Unit). In a memory management mechanism (MMU), memory management is generally performed by a virtual storage method. Virtual storage is a means for dividing and using physically limited memory in many processes (computer architecture, David A. Patternson, Jo).
hn L.H. Hennessy, 1993, pp43
7-456). That is, the physical memory is divided into a plurality of blocks, and the blocks are allocated to each process.

[0005] Before the concept of this virtual memory was devised, if the program exceeded the capacity of the physical memory, the programmer had full responsibility for enabling the program to be executed in that capacity. That is, first, the program is divided into small pieces to find mutually exclusive ones. The order in which these overlay portions are loaded into the main memory is all controlled by the user's program. The programmer must ensure that the operation does not exceed the physical memory limit during execution.

[0006] Such a factor has hindered the productivity of the programmer. A virtual memory has been devised for the purpose of relieving the programmer from such difficulties, and a mechanism for providing the programmer with a virtual address space that is larger and continuous than the physical memory to be mounted.

FIG. 4 shows a virtual address conversion method in a conventionally used virtual storage method. The virtual address (1000) is the virtual page address (10
01) and the offset within the page (1
002). The virtual address space and the physical memory space are offset by an offset within the page (1
002). In the virtual address space, as many pages as the number indicated by the virtual page address (1001) exist.

Which page in the virtual address space is allocated to which page in the physical memory space is managed by a page table (1103). A page table base (1101) which is an address serving as a base point of the page table;
The page table limit (1102), which is the value of the table size, is stored in each system register. To generate a physical address from a virtual address, the virtual page address (1001) of the virtual address and the page table base (1101) are added by an adder (1105), and one page in the page table is added based on this value. Table entry (110
4) is specified.

At this time, it is confirmed that the output of the adder (1105) does not exceed the page table limit (1102) (1).
106). If this value is exceeded, an error is detected. The virtual page address in the physical address space is extracted from the specified page table entry (1104) and combined with the in-page offset of the virtual address to generate the physical address (1100). The physical address such as the main memory is accessed by the physical address (1100).

In this virtual memory system, the number of pages handled in the physical memory space is naturally smaller than the number of pages handled in the virtual address space. Therefore, when a program accesses a page in a virtual address space that is not in the physical memory, a page fault occurs. When a page fault occurs, a process of adding a new page table entry or loading a program from a secondary storage (disk or the like) to a physical memory is required. A series of processes associated with a page fault need not be conscious of a user program, and is generally placed under the control of an operating system.

Further, as a hardware mechanism for converting this virtual address at high speed, a TLB (Tr
analysis Lookaside Buffet
r). The TLB is a page table (110
3) It is like a cache memory, and instead of accessing the page table at a virtual address, the processor
Address conversion can be performed at high speed by accessing the TLB.

In the following, a full set associative method shown in FIG. 5 (selection of an entry is performed by hitting a built-in comparator for each entry in the TLB without decoding a part of the virtual address and performing entry selection) Configuration)
The TLB (1051) will be described. TLB (10
51) are 0 to N sets of page table entries (P
TE) (1061-0 to N). Each P
The TE can have a copy of the page table entry in the page table shown in FIG. Each PTE includes a tag field (1052), a data field (1053), and an address comparator (1054).

The tag field (1052) has the following 2
It is composed of fields (a) and (b). (A) VPA [31:12]: Virtual Page
e Address (virtual page address) (b) ASID: Address Space ID
(Address Space ID) The OS realizes a multiple virtual address space by managing the ASID for each process.

The data field (1053) is
It is composed of the following seven fields (c) to (i). (C) PPA [31:12]: Physical Pa
ge Address (physical page address) Holds a physical page address corresponding to the minimum page size of 4 kB. The used size is changed according to the page size indicated by the PZ field. 4kB page: not using PPA [31:12] all 16kB page: not using PPA [13:12] 64kB page: not using PPA [15:12] 128kB page: not using PPA [17:12]

(D) N: Non Cacheable A
rear bit (non-cacheable bit) 0 = cacheable area 1 = cacheable area (e) AC [2: 0]: Access Control
bits (access control bits) AC [2]: 0 = Read accessible, 1 = Read unavailable AC [1]: 0 = Write accessible, 1 = Write disabled AC [0]: 0 = Executable, 1 = Not executable

(F) PZ [1: 0]: Page siz
e bits (page size bit) 00 = 4 kB size 01 = 16 kB size 10 = 64 kB size 11 = 128 kB size (g) M: Modify bit (change bit) 0 = no write access occurred 1 = write access occurred

(H) G: Global Page bi
t (global page bit) 0 = local page 1 = global page (i) V: Entry Valid bit (valid bit) 0 = invalid entry 1 = valid entry

An address comparator (1054) in each PTE
Is for checking whether a page table entry for a virtual page of a memory access destination generated by a program is registered in the TLB. The ASID for the currently executed process and the virtual page address for the memory access generated in this process are input from the path 1050 to the address comparator (1054). Further, the VP of the tag field (1052)
A, ASID, and P of the data field (1053)
Z, G, and V are input.

The comparison between the virtual page address from the path 1050 and the VPA of the tag field (1052) (referred to as “comparison A”) is performed based on the page size by PZ. The comparison between the ASID from the path 1050 and the ASID of the tag field (1052) (referred to as “comparison B”) is valid only when the G bit is 0. The results of these comparisons A and B are valid only when the V bit is 1, and if the V bit is 0, the comparison results unconditionally do not match.

In all PTE address comparators,
If the comparison results do not match (TLB miss), the occurrence of the TLB miss is transmitted to the exception detection mechanism via the path 1055. The exception detection mechanism informs the processor core that exception handling due to a TLB miss is required. A TLB miss means that the page table entry for the virtual page is not registered in the TLB. Therefore, in this exception handling routine, a series of processes for registering the page table entry in which the TLB miss has occurred in the TLB from the path 1059 is performed, and the process of returning to the instruction in which the TLB miss occurred in order to re-execute the memory access is performed. Do.

If the comparison result in any of the address comparators of the PTEs matches (TLB hit), the output control unit (1) reports that the TLB hit has occurred due to the path 1055.
056). In the output control unit (1056), the PPA of the hit data field in the PTE is output (1057) and used to generate a physical address. At the same time, N and AC of the data field in the hit PTE are output to the control unit of the memory management unit. N
If the bit is set (= 1), a process is executed so that data accessed at the generated physical address is not registered in the cache memory. The AC bit is used to detect an exception to the access performed using the generated physical address.

If the access performed using the generated physical address is a write process, it indicates that the physical page has been changed, and this information is set by setting M bits by the path (1060). Is performed. Normally, when the physical page is paged out of the physical memory, if the M bit is set,
A process of writing back the contents of the physical page to the secondary storage is performed.

The address conversion processing based on the virtual memory system using the TLB occurs from the processor core by instruction fetch and operand access. In recent years, the processing speed of processors has been remarkably improved, and those operating at several hundred MHz are not uncommon.

On the other hand, the access speed of the main memory is
It's still late, without letting the processor wait,
In order to execute the processing continuously, a cache memory or a built-in memory is used. In addition, the capacities of these cache memories and built-in memories tend to gradually increase in order to improve processor performance.
Therefore, in the instruction fetch and operand access from the processor core, the address translation process is performed by TLB,
In addition, it is required to execute a cache memory or a built-in memory access at a high speed.

FIG. 6 shows an address translation process in the TLB,
4 shows a processing flow for executing read access to a physical cache memory in parallel. Reference numeral 1010 denotes a memory management mechanism, which incorporates a TLB and is capable of high-speed address translation. Reference numeral 1020 denotes a cache memory, which is accessed using a physical address after the address conversion. The cache memory (1020) includes a decoding unit (1021) for selecting an entry and a tag unit (1010) for holding a tag address.
22), a mode part (1023) for holding a valid bit or the like indicating that the entry is valid, a data part (1024) for holding data, and an address comparator (102).
5) and an output control unit (1026).

The size of the data section is determined by the decoding section (102
The entry address (1004) input to 1) and 1
It is determined by the total size of the address (1005) indicating the block data size registered in the entry. For example, if the block size is 16 bytes (= 2 ⁴ ) and 256
In the case of an entry (= 2 ⁸ ), the size of the data portion (the size obtained by multiplying the block data size by the entry size is called a set size) is 4 kB (= 2
¹² ) In the configuration of the cache memory shown in FIG.
The set size is smaller than the page size of the virtual address.

Only the virtual page address (1001) of the virtual address (1000) is input to the TLB in the memory management mechanism (1010), and the physical page address (1006) is output after the TLB hit. The in-page offset (100
The address (1004) of 2) is the decoding unit (1021)
And one entry in the cache memory is selected. The selected tag address (1027) is added to the address comparator (1025) together with the mode bit (1029).
To the address of the offset within the page (100
3) is compared with the physical page address (1006) output from the memory management mechanism.

If the comparison result in the address comparator (1025) matches (cache hit), the block data (1028) in one entry selected in the data section is output from the output control section (1026). . If the comparison result in the address comparator (1025) does not match (cache miss), read access to the physical memory is continuously performed using the physical page address (1006) generated by the memory management mechanism (1010).

As described above, when the set size of the cache memory is smaller than the page size of the virtual address, it is not necessary to decode the entry selection of the cache based on the result of the address conversion by the memory management mechanism (1010). , A series of processes can be executed at high speed. Therefore, in order to realize the processing flow as shown in FIG.
The minimum page size handled by the TLB needs to be set larger than the set size of the cache memory.

However, as the capacity of the cache memory increases, the minimum page size supported by the TLB increases (for example, when a cache memory of 32 kB is built in, even if the 4-way set associative is used, one set size is required). Is 8 kB. Accordingly, the minimum page size supported by the TLB is 8 kB), which may hinder precise memory management. For example, when general-purpose memories (SRAM, DRAM) are built in the same chip as the cache memory, if a large page size is allocated to these general-purpose memories, the memory usage efficiency may decrease.

A major reason for incorporating these general-purpose memories is to perform high-speed memory access.
I want to improve the performance of the processor by improving the use efficiency of the built-in general-purpose memory as much as possible. Therefore, a mechanism that supports a page size smaller than the set size of the cache memory in the TLB is required.

FIG. 7 is a processing flow in the case where address conversion and read access to the cache memory are performed with a virtual address having a page size smaller than the set size of the cache memory. The configuration of the cache memory (1020) is exactly the same as that shown in FIG. The sum of the address (1004) for specifying the entry and the address (1005) for specifying the block data size is the offset within the page (100) indicating the page size of the virtual address.
2), and the address (1008) exceeding the address becomes a target of address conversion in the TLB in the memory management mechanism (1011).

For this reason, the cache memory (1020)
It is necessary to input a part (1009) of the physical page address (1006) output from the memory management mechanism (1011) to the decoding unit (1021) for selecting the entry of (1). Thus, the memory management mechanism (101
Only after the address conversion in 1), the decoding process for selecting an entry in the cache memory can be started.
As a result, the processing speed is reduced.

[0034]

SUMMARY OF THE INVENTION An object of the present invention is to improve the efficiency of use of a built-in general-purpose memory in a system LSI having a cache memory and a general-purpose memory.

[0035]

A memory management system according to the present invention is provided in a processor having a main storage device and a cache memory, and the processor mainly uses a physical page address obtained by replacing an input virtual page address. In a memory management method in which a virtual page address is replaced with a physical page address when referring to a storage device, a virtual page address is input, and a page size of a page specified by the physical page address obtained by replacing the input virtual page address and Comparing the size of the cache memory with a non-cacheable control unit for instructing whether to register the page specified by the physical page address in the cache memory based on the comparison result. I do.

The non-cacheable control unit does not register the page specified by the physical page address in the cache memory when the page size of the page specified by the physical page address is smaller than the size of the cache memory. Is indicated.

The memory management method further includes a virtual page address, a physical page address corresponding to the virtual page address, page size data indicating a page size of a page specified by the physical page address, A non-cacheable data indicating a value specifying whether to register or not register the page specified by the address in the cache memory; and a non-cacheable control unit, wherein the non-cacheable control unit stores When the value indicates that the size is smaller than the size of the cache memory, a value designating not to be registered is set in the non-cacheable data.

[0038] The processor further includes a memory management control unit that manages a cache memory. The non-cacheable control unit further includes a page size of a page specified by the physical page address and a size of the cache memory. And a registration data check unit for outputting to the memory management control unit a signal indicating whether to register the page specified by the physical page address in the cache memory or not based on the result of the comparison. It is characterized by.

The registration data check unit instructs not to register the page specified by the physical page address in the cache memory when the page size of the page specified by the physical page address is smaller than the size of the cache memory. And outputting a signal to the memory management control unit.

[0040]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 In the memory management method for the built-in memory of the present invention, in a system LSI having a built-in cache memory and a general-purpose memory, a TLB supports a page size smaller than the set size of the cache memory in order to improve the use efficiency of the built-in general-purpose memory. It is related to the mechanism that performs. The set size is
It indicates the size of the cache memory (the size of the data portion of the cache memory), and is specifically a value of the product of the block data size and the number of entries.

FIG. 1 shows an example of a memory management mechanism (memory management system) for a built-in memory according to this embodiment. 10
0 is a system LSI of this embodiment. 102
Reference numeral 0 denotes a cache memory built in the system LSI, which has the same configuration as the conventional cache memory shown in FIGS. The size (set size) of the data part (1024) in the cache memory (1020) is 4
kB. 103 is a 3 built-in system LSI.
2 kB internal memory. Reference numeral 110 denotes a page mapping state in the internal memory.

Reference numeral 101 denotes a memory management mechanism (memory management system) according to this embodiment, which comprises a TLB (1) and a memory management control unit (30). TLB (1)
Has a tag field (3) and a data field (4). Furthermore, the TLB (1) has a built-in non-cacheable control unit (11).

The non-cacheable control unit (11) inputs a virtual page address, and sets the page size of the page specified by the physical page address obtained by replacing the input virtual page address, the size of the cache memory (set size), and the like. And instructs, based on the result of the comparison, whether to register the page specified by the physical page address in the cache memory.

In the memory management control unit (30), a TLB maintenance unit (3
1) various controls such as a cache access control unit (32) for controlling access to the cache memory (1020), a built-in memory control unit (33) for controlling the built-in memory, and an exception detection unit (34) for detecting an exception. Includes components to perform.

Reference numeral 102 denotes a bus interface unit (BIF) for controlling data access between the system LSI (100) and the external memory (104). Reference numeral 104 denotes an external memory (external physical memory), and reference numeral 111 denotes a page mapping state in the external memory. 105
Indicates a secondary storage device such as a hard disk.

Next, a description will be given of a memory read access process started from a processor core (built-in to the system LSI; not shown in FIG. 1). The memory access from the processor core is output to the memory management mechanism (101) at a virtual address. In the memory management mechanism (101), the input virtual address is
The address is converted by LB (1) (in the case of a TLB hit),
Generate a physical address. The generated physical address is
The data is output from the memory management mechanism (101) to the cache memory (1020) through the bus (120). On the other hand, a signal (12
1) is returned.

In the case of a cache hit, the target data read from the cache memory is
Transferred to the memory management mechanism through 2). Then, the target data is transferred from the memory management mechanism (101) to the processor core, and the memory access process started from the processor core is completed.

In the case of a cache miss, the bus (123)
Physical address through built-in memory (103) and BIF
Output to (102). If the physical address points in the internal memory, the target data is output through the bus (124). This target data is input to the memory management mechanism (101) via the bus (126). Then, the data is transferred to the processor core, and a series of memory access processing is completed.

If the physical address does not point in the internal memory, the BIF (102) outputs the physical address to the external memory through the bus (130), and obtains the target data from the external memory through the bus (131). . Then, the BIF (102) transfers the target data to the memory management mechanism through the bus (125) and the bus (126). Then, the data is transferred to the processor core, and a series of memory access processing is completed.

If the target data is to be cached, the memory management mechanism (101) sets the bus (127)
The physical address and the target data used in the access are registered in the cache memory (1020) through the cache memory (1020). The case where a TLB hit occurs due to memory access started from the processor core has been described above.

On the other hand, when a TLB miss occurs due to memory access, the OS fetches a page table entry for address translation from the page table managed on the physical memory, and executes the TL.
B and re-execute the memory access. If a TLB miss occurs due to a memory access and there is no page table entry for address conversion in the page table, a process (page-in) of loading the target page from the secondary storage (105) into the physical memory is required. .

In the above-described processing for registering a new page table entry in the TLB and processing for newly loading a target page in the physical memory, if there is no extra area, replacement processing and page-out processing are required, respectively. Becomes Regarding these various processes at the time of TLB mistake,
Detailed description is omitted because it is not essential to the present invention.

The non-cacheable control unit (11) and each control (30) mechanism in the memory management mechanism (101) have a set size (the cache memory (1020) in FIG. 1) which is the size of the data section of the cache memory (1020). ) Is required when dealing with pages smaller than (the set size is 4 kB). The internal memory, which has a smaller capacity than the external memory but can be accessed at a high speed from the processor core, can handle more pages as small as 1 kB, as shown in the page mapping example of 110. It is possible to store the data on the built-in memory, and the use efficiency of the memory is improved.

However, as shown in the conventional example of FIG.
In a configuration in which LB address conversion and cache memory access are performed in parallel, it is impossible to handle a page smaller than the set size of the cache memory. Therefore, in the present invention, when a page smaller than the set size of the cache memory is handled in the built-in memory, a non-cacheable control unit (11) is provided as a control mechanism for forcibly setting this page to a non-cacheable area. ing.

FIG. 2 shows an example of a memory management mechanism for a built-in memory according to the present invention. Reference numeral 1 denotes a full set associative method similar to that shown in FIG. 5 (a configuration in which a part of a virtual address is not decoded and entry selection is performed, but an entry is selected by hit / miss of a built-in comparator for each entry in the TLB ) TLB. TLB (1) is a set of page table entries (PTE) (2-0 to N) of 0 to N sets
It is composed of Each PTE can have a copy of the page table entry in the page table shown in FIG. Each PTE includes a tag field (3), a data field (4), and an address comparator (5).

The tag field (3) is composed of the following two fields (j) to (k). (J) VPA [31:10]: Virtual Page
e Address (virtual page address) (k) ASID: Address Space ID
(Address space ID) The OS realizes a multiple virtual address space by managing the ASID for each process.

The data field (4) is composed of the following seven fields (l) to (r). (1) PPA [31:10]: Physical Pa
“ge Address” (physical page address) The physical page address corresponding to the minimum page size of 4 kB is held. The used size is changed according to the page size indicated by the PZ field. 1 kB page: not using PPA [31:10] all 4 kB page: not using PPA [11:10] 16 kB page: not using PPA [13:10] 64 kB page: not using PPA [15:10]

(M) N: Non Cacheable A
rear bit (non-cacheable bit) 0 = cacheable area 1 = cacheable area (n) AC [2: 0]: Access Control
bits (access control bits) AC [2]: 0 = Read accessible, 1 = Read unavailable AC [1]: 0 = Write accessible, 1 = Write disabled AC [0]: 0 = Executable, 1 = Not executable

(O) PZ [1: 0]: Page siz
e bits (page size bit) 00 = 1 kB size 01 = 4 kB size 10 = 16 kB size 11 = 64 kB size (p) M: Modify bit (change bit) 0 = no write access occurred 1 = write access occurred

(Q) G: Global Page bi
t (global page bit) 0 = local page 1 = global page (r) V: Entry Valid bit (valid bit) 0 = invalid entry 1 = valid entry

The address comparator (5) in each PTE is for checking whether a page table entry for a virtual page of a memory access destination generated by a program is registered in the TLB. The address comparator (5) has an ASID for the currently executing process,
The virtual page address for the memory access generated in this process is input from the path 20. further,
VPA and ASID of the tag field (3) and PZ, G and V of the data field (4) are input.

Comparison of virtual page address from path 20 and VPA of tag field (3) (referred to as “comparison C”)
Is performed based on the page size by PZ. The comparison between the ASID from the path 20 and the ASID of the tag field (3) (referred to as “comparison D”) is as follows.
Valid only when. The results of Comparison C and Comparison D are as follows:
It is valid only when the V bit is 1, and if the V bit is 0, the comparison result unconditionally does not match.

In all PTE address comparators,
If the comparison results do not match (TLB miss), the fact that a TLB miss has occurred through the path 6 is transmitted to the exception detection mechanism. The exception detection mechanism informs the processor core that exception handling due to a TLB miss is required. TL
B miss indicates that the page table entry for the virtual page is TL
B means not registered. Therefore, in this exception handling routine, a series of processes for registering the page table entry in which the TLB miss has occurred from the path (9) to the TLB are performed, and the TL is used for re-executing the memory access.
A process for returning to the instruction in which the B miss has occurred is performed.

If the comparison result of any of the address comparators of the PTEs matches (TLB hit), the fact that the TLB hit has occurred through the path 6 is transmitted to the output control unit (7). In the output control unit (7), the PPA of the data field in the hit PTE is output (8) and used to generate a physical address. At the same time, N and AC of the data field in the hit PTE are output to the control unit of the memory management unit. If the N bit is set (= 1), a process is performed so that data accessed with the generated physical address is not registered in the cache memory. The AC bit is used to detect an exception to the access performed using the generated physical address.

If the access performed using the generated physical address is a write process, it indicates that the physical page has been changed, and this information sets M bits according to the path (10). Is performed. Normally, when the physical page is paged out of the physical memory, if the M bit is set, the OS performs a process of writing back the contents of the physical page to the secondary storage.

Further, in the TLB (1) of this embodiment, the PZ value of the data field (4) in the PTE is 00
, That is, when handling a page of 1 kB size,
The NOR circuit (14) becomes High and the OR circuit (15)
, The non-cacheable signal (12) is forcibly set to H regardless of the value of the non-cacheable bit N.
high, and this page is controlled as a non-cacheable area.

The non-cacheable control unit (1
By providing 1), the OS can handle a page of 1 kB size without being conscious of whether the page size is smaller than the set size of the cache memory, thereby improving the use efficiency of valuable internal memory resources. It becomes possible.

Embodiment 2 In this embodiment, a case will be described in which the non-cacheable control unit (11) includes a registration data check unit (35). FIG. 3 shows an example of a memory management mechanism for a built-in memory according to this embodiment.

Reference numeral 1 denotes a TLB. Blocks indicated by the same numbers as those of the TLB shown in FIG. 2 perform the same processing.
In the memory management mechanism for a built-in memory of the present invention shown in FIG. 3, the OS stores the page table entry shown in FIG.
Page (PZ = 00) smaller than the set size of the cache memory without setting the non-cacheable bit (N = 0) when registering in the PTE (2-0 to N) in the path (9). State), when registration is attempted, registration processing is performed through a registration data check unit (35) as a mechanism for checking registration data.

When the page size of the page specified by the physical page address is smaller than the cache memory size (set size), the registration data check unit (35) registers the page specified by the physical page address in the cache memory. A signal instructing not to be output is output to the exception detection unit (34) of the memory management control unit (30).

In this embodiment, the registration data check unit (35) recognizes, as an exception, if the OS attempts to perform PTE registration when PZ = 00 and N = 0, the memory management A signal (36) is transmitted to the exception detection mechanism of the control unit (30). If the OS attempts to perform PTE registration when the registration data check unit (35) has a combination of PZ = 00 and N = 0, it is forcibly changed to N = 1 and then PZ = 00. And N = 1 can be set to perform PTE registration. By providing such a registration data check unit (35), the OS can handle a page of 1 kB size without being conscious of whether the page size is smaller than the set size of the cache memory.
It is possible to improve the use efficiency of the valuable internal memory resources.

Embodiment 3 In the above embodiment, the non-cacheable control unit (11) sets the PZ (page size bit) to the set size (cache memory size).
The case where the page specified by the physical page address is forcibly excluded from the registration target in the cache memory when the size is smaller than the above is described. However, the present invention is not limited to this. The non-cacheable control unit (11) can compare the PZ with the set size and set the non-cacheable bit (N) based on the result of the comparison.

The non-cacheable control unit (11)
Is not limited to setting the non-cacheable bit (N), and the registration in the cache memory may be controlled by using a mechanism for controlling the registration in the cache memory.

Similarly, the registration data check unit (35) described in the third embodiment also compares the PZ with the set size without being limited to the case where the PZ is smaller than the set size. Based on this, the signal 36 may be output. Also, the signal 36 is not limited to a signal whose page specified by the physical page address is not to be registered in the cache memory, and may output a signal having another meaning.

Embodiment 4 In the first embodiment, the non-cacheable control unit (1
1) has described the case where it is inside the TLB (1). However, the non-cacheable control unit (11)
It may be outside the LB. The non-cacheable control unit (11) only needs to exist in the memory management mechanism (101).

Similarly, in FIG. 3 of the second embodiment, the registered data check unit (35) shown as an example of the non-cacheable control unit (11) also has a TLB.
It may be outside of (1). The registration data check unit (35) is also a memory management mechanism (101)
What is necessary is just to exist within.

[0077]

According to the present invention, registration of a physical page in a cache memory can be controlled.

According to the present invention, by forcibly stopping the registration of the physical page in the cache memory, the page can be handled without being aware of the page size, and the use efficiency of the storage area can be reduced. Can be improved.

According to the present invention, the signal that checks the physical page size and controls the registration of the physical page in the cache memory enables the OS to handle the page without being aware of the page size. Thus, the use efficiency of the storage area can be improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a virtual address translation method in a virtual storage method according to an embodiment.

FIG. 2 is a diagram illustrating an example of a configuration in which a non-cacheable control unit according to the embodiment is added to a TLB.

FIG. 3 shows a registration data check unit of this embodiment as T
The figure showing an example of the structure added to LB.

FIG. 4 is a configuration diagram illustrating a virtual address translation method in a conventional virtual storage method.

FIG. 5 is a diagram showing an example of a TLB in a conventional virtual storage system.

FIG. 6 is a configuration diagram illustrating a virtual address translation method in a conventional virtual storage method.

FIG. 7 is a configuration diagram illustrating a virtual address translation method in a conventional virtual storage method.

[Explanation of symbols]

1 TLB, 2, 2-0 to n PTE, 3 tag fields, 4 data fields, 5 address comparators,
6, 9, 10, 20, 1050, 1055, 1059,
1060 path, 7 output control unit, 8,1057 output, 11 non-cacheable control unit, 12 non-cacheable signal, 14 NOR circuit, 15 OR circuit, 3
0 memory management control unit, 31 TLB maintenance unit, 32 cache access control unit, 33 built-in memory control unit, 34 exception detection unit, 35 registration data check unit, 36 signals, 100 system LSI, 101 memory management mechanism, 102 bus interface unit (BIF), 103 internal memory, 104 external memory, 105 secondary storage device, 110 page mapping state, 120, 122 to 127, 130, 131 bus, 121 signals, 1000 virtual addresses, 1001
Virtual page address, 1002 offset within page, 1004 entry address, 1005 block data size address, 1006 physical page address, 1010, 1011 memory management mechanism, 102
0 cache memory, 1021 decoding unit, 102
2 Tag section, 1023 mode section, 1024 data section, 1025 address comparator, 1026, 1056
Output control unit, 1027 tag address, 1028 block data, 1029 mode bit, 1051 TL
B, 1052 tag field, 1053 data field, 1054 address comparator, 1061-0 to 1
061-N Page Table Entry (PTE), 11
00 physical address, 1101 page table base, 11
02 page table limit, 1103 page table, 1104 page table entry, 1105 adder, 1106 comparator.

Claims (5)

[Claims] 1. A processor having a main memory and a cache memory, wherein a virtual page address is replaced with a physical page when the processor refers to the main memory using a physical page address obtained by replacing an input virtual page address. In the memory management method of replacing an address, a virtual page address is input, and the page size of a page specified by a physical page address replacing the input virtual page address is compared with the size of the cache memory. A non-cacheable control unit for instructing whether or not to register a page specified by the physical page address in the cache memory based on the above. 2. The non-cacheable control unit registers a page specified by the physical page address in the cache memory when a page size of the page specified by the physical page address is smaller than a size of the cache memory. 2. The memory management method according to claim 1, wherein an instruction is given not to do so. 3. The memory management method further comprises: a virtual page address, a physical page address corresponding to the virtual page address, page size data indicating a page size of a page specified by the physical page address, A page table entry for storing non-cacheable data indicating a value specifying whether to register or not register a page specified by a physical page address in the cache memory; the non-cacheable control unit includes: 3. The memory management method according to claim 1, wherein when the value is smaller than the size of the cache memory, a value designating no registration is set in the non-cacheable data. 4. The processor further includes a memory management control unit that manages a cache memory, the non-cacheable control unit further includes a page size of a page specified by the physical page address, and a memory size of the cache memory. A registration data check unit that compares the size with the memory management control unit and outputs a signal indicating whether to register the page specified by the physical page address to the cache memory or not based on the comparison result to the memory management control unit 2. The memory management system according to claim 1, wherein: 5. The registration data check unit according to claim 1, wherein a page size of the page specified by the physical page address is smaller than a size of the cache memory.
5. The memory management method according to claim 4, wherein a signal indicating that a page specified by a physical page address is not registered in the cache memory is output to the memory management control unit.