JPH086857A - Cache memory - Google Patents

Abstract

PURPOSE:To improve the yield by dividing a tag memory into an (a)-bit memory part for storing the high-order (a) bits of (n) bits of a tag address and a (b)-bit memory part for storing the low-order (b) bits, and providing the single (a)-bit memory part in common to all entries. CONSTITUTION:The cache memory is constituted by dividing the tag memory 9 into the 17-bit memory part 9a and 3-bit memory part 9b, and the single 17-bit memory part 9a is provided in common to all the entries of a data memory 7. Then the high-order 17 bits of the tag address 1a of data which are cached first are stored in the 17-bit memory part 9a of the tag memory 9 and only data having matching high-order 17 bits of the tag address 1a can be cached thereafter. Consequently, the contents of the 17-bit memory 9a are fixed to the high-order 17 bits unless all the data in the data memory 7 are made ineffective, and data can be cached only when the 17 bits match.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory in which used data is stored together with its address, and when the data at the same address is needed again, the corresponding data is read out.

[0002]

2. Description of the Related Art Generally, an information processing system sequentially reads data from a main storage device and supplies the data to a control unit to perform data processing. However, the main storage device has a slow access speed, and the data processing speed is slowed down. Become. Therefore, by storing already used data together with the address in a memory that operates faster than the main storage device, when the data at the same address is needed again, the corresponding data can be quickly read to the control unit. As a result, the data processing of the information processing system can be speeded up. Therefore, a cache memory is used to store a plurality of data and the address of each data.

FIG. 4 is a block diagram showing a main structure of a conventional cache memory which is generally used. In addition,
Although an actual cache memory requires various control circuits in addition to them, they are omitted in FIG. 4 for convenience. The address 1 of the predetermined data in a micro processing unit (hereinafter referred to as MPU) (not shown) is the tag address 1a of the upper 20 bits in the address 1 and the entry address of the lower 8 bits following the tag address 1a in the address 1. It consists of 1b. The entry address 1b is input to the entry decoder 2 which converts the entry address 1b into a signal designating an actual entry in the cache memory.

The 20-bit tag address 1a is 20 bits × 25
Tag memory with comparison function with a storage capacity of 6 entries 3
Is input to. Entry address to entry decoder 2
As a result of decoding by, the entry designation signal designated is 1
It is input to the valid bit 4 of bit × 256 entries, the data write / read circuit 6, the tag memory 3 and the data memory 7. In the tag memory 3 with the comparison function, the hit signal is generated in the hit signal generation unit 5 based on the comparison result of the stored tag address and the input tag address and the value of the valid bit 4, and the hit signal is generated. The hit signal HT output from the generation unit 5 is input to the control unit 8 which controls the reading of data according to the value of the hit signal HT.

The data write / read circuit 6 can write / read data to / from the data memory 7 having a storage capacity of 256 entries. The data writing and reading circuit 6 is input data DT _W to be written to the data memory 7, the data DT _R read out from the data memory 7 is adapted to be read through the control unit 8.

Next, the operation of the cache memory will be described. At the time of writing data to the cache memory, as a result of decoding the 8-bit entry address 1b by the entry decoder 2, data DT _W is written to the data memory 7 via the data write / read circuit 6 for the specified entry. Then, the tag address 1a is written in the tag memory 3. When reading data, the entry address
As a result of decoding 1b by the entry decoder 2, the valid / invalid judgment of the data by the valid bit 4 and the tag address 1a and the data in the tag memory 3, that is, the tag address of the data already used, are determined for the specified entry. If the comparison result is valid and the tag address 1a matches, the hit signal HT generated by the hit signal generation unit 5 becomes active and the control unit 8
Given the readout data DT _R is read out to the outside through the control unit 8 by the data writing and reading circuit 6.

As described above, the conventional cache memory corresponds to the data memory 7 for storing the data used in the past and has the same number of tag addresses 1a as the number of entries.
It is equipped with a tag memory 3 for storing all 20 bits of.

[0008]

However, the provision of the tag memory for storing all the tag addresses from the MPU for the data of each entry stored in the data memory 7 as described above is as follows. There is a problem that the storage capacity of the tag memory becomes significantly large, and when integrated, it occupies a relatively large area on the chip and causes a reduction in the yield of the cache memory. In view of such a problem, it is an object of the present invention to provide a cache memory that can reduce the area of the tag memory on the chip and improve the yield.

[0009]

A cache memory according to a first aspect of the present invention comprises a tag memory having an a-bit memory section for storing upper a bits of a tag address n bits and a b-bit memory section for storing lower b bits (a + b). = N, a, b, n
Is an integer), and a single a-bit memory unit is provided for all entries of the data memory.

A cache memory according to a second aspect of the present invention is a tag memory unit having a storage capacity for one entry for storing n bits of a tag address, and a valid bit unit for determining validity / invalidity of data for all entries. A plurality of tag memory units each including and are provided.

[0011]

In the first aspect of the invention, the high order a of n bits of the tag address is used.
The bits are stored in the a-bit memory section common to each entry. The lower b bits following the upper a bits are stored in the b bit memory unit corresponding to the entry. When the contents stored in the a-bit memory section and the b-bit memory section of the entry specified by the entry address match the tag address, the data read from the data memory of the entry specified by the entry address is read out to the outside. It As a result, the area of the tag memory on the chip is reduced, and the yield of the cache memory is improved.

In the second invention, the tag address n bits are
The data is stored in the tag memory unit having a storage capacity of one entry in the tag memory unit. Valid / invalid of data of each entry is judged by valid bit. When the content stored in the tag memory unit matches the tag address and the entry data is determined to be valid, the data read from the data memory of the entry specified by the entry address is read to the outside. The number of tag memory units is sufficiently smaller than the number of data memory entries. As a result, the area of the tag memory on the chip is reduced, and the yield of the cache memory is improved.

[0013]

The present invention will be described in detail below with reference to the drawings showing the embodiments thereof. FIG. 1 is a block diagram showing a configuration of a main part of a cache memory according to the present invention. The address 1 of the predetermined data in the MPU (not shown) is the higher order of the addresses 1.
It consists of a 20-bit tag address 1a and an 8-bit entry address 1b following the tag address 1a in address 1. The entry address 1b is input to the entry decoder 2 which converts the entry address 1b into a signal designating an actual entry in the cache memory. The 20-bit tag address is input to the tag memory 9 with a comparison function. The tag memory 9 is, for example, the higher order of the 20 bits of the tag address 1a.
17-bit memory section 9a into which 17 bits are input, and 3-bit memory section into which lower 3 bits following the upper 17 bits are input
It consists of 9b. The 17-bit memory unit 9a is provided as a single unit common to all the 256 entries of the data memory 7 described later.

The 3-bit memory unit 9b is a memory of the data memory 7.
It is provided corresponding to each of the 56 entries. The tag memory 9 is provided with a valid bit 4 for judging the validity / invalidity of the data of all entries of the data memory 7, and the tag memory 9 compares the tag address 1a with the contents of the tag memory. , A hit signal generation unit 5 for generating a hit signal HT according to the determination result of the valid bit 4 is provided. The hit signal HT output from the hit signal generation unit 5 is input to the control unit 8 which controls the output of data according to the hit signal HT.

[0015] Data write and read circuit 6, writing data DT _W for the entry specified by the entry address of the data memory 7 is input, for the entry specified by the entry address of the data memory 7, data data DT _R which is read by the write and read circuit 6 is adapted to be read to the outside through the control unit 8. In addition,
An actual cache memory has various control circuits other than these, but they are omitted here for convenience.

Next, the operation of the cache memory thus configured will be described. Now, when valid data is not stored in the data memory 7 at the time of writing data to the cache memory, as a result of decoding the 8-bit entry address 1b by the entry decoder 2 data DT _W via the data writing and reading circuit 6 to the memory 7, also the 3-bit memory portion 9b of the tag memory 9 the lower 3 bits of the tag address 1a is written people write respectively. Further, the upper 17 bits of the tag address 1a are written in the 17-bit memory 9a which is common to all the entries of the data memory 7.

However, when valid data is already stored in the data memory 7 when writing data to the cache memory, the upper 17 bits of the tag address 1a and 17
When the contents of the bit memory unit 9a are compared and the comparison result is a match, the 8-bit entry address 1b is decoded by the entry decoder 2, and as a result, the data memory The data DT _W is written in the data 7 via the data write / read circuit 6, and the lower 3 bits of the tag address 1a are written in the 3-bit memory section 9b.

However, if the comparison result of the upper 17 bits of the tag address 1a and the content of the 17-bit memory section 9a does not match, no data is written to the data memory 7, No data is cached.

When reading data from the cache memory, the entry address 1b is set to the entry decoder 2
As a result of decoding in step 3, the valid / invalid judgment of the data by the valid bit 4 and the lower 3 bits of the tag address 1a and the content of the 3-bit memory section 9b are performed for the specified entry, and the tag address Compare the upper 17 bits of 1a with the contents of the 17-bit memory section 9a,
Data of the determination result is valid, and both the comparison result from the hit signal generator 5 when being output hit signal HT is a match, the data DT _R read out through the data writing and reading circuit 6 is a control unit 8 It is read out to the outside via.

As described above, in the cache memory shown in FIG. 1, the tag memory 9 is divided into the 17-bit memory section 9a and the 3-bit memory section 9b, and the 17-bit memory section 9a is replaced by the data memory 7. Since the single entry is commonly provided for all entries, the area of the tag memory 9 on the chip can be reduced, and as a result, the yield of the cache memory can be improved.

In this way, in the cache memory, the 17-bit memory section 9a of the tag memory 9 stores the upper 17 bits of the tag address 1a of the first cached data, and thereafter, the higher order of the tag address 1a of the data. Only data whose 17 bits match can be cached. Therefore, unless a situation occurs in which all the data in the data memory 7 becomes invalid, the contents of the 17-bit memory section 9a of the tag memory 9 is fixed at the upper 17 bits of the tag address of the first cached data. As a result, data will be cached only when the 17 bits match thereafter.

Further, the cache memory has a temporal locality that a data accessed at a certain point is likely to be accessed again in the near future in a program whose normal principle is normal, and the cache memory has a local area near the accessed data. It takes advantage of the spatial locality that data is likely to be accessed. According to this spatial locality, in the normal program execution, the address of the data to be accessed next is a relatively close address, so the address of the data currently being accessed differs from the low-order bits of the address. However, there are many cases where the upper addresses are common. Therefore, for example, the top of the tag address
Fixing 17 bits causes almost no trouble.

However, with respect to data in the vicinity where the lower address is 0 ... 0, 1 ... 1 and the upper address also changes, the ratio of cases in which caching is not possible increases, which may cause a problem. Such a problem can be solved by using the configuration of the cache memory shown in FIG.

FIG. 2 is a block diagram showing the configuration of another embodiment of the cache memory according to the present invention. Tag address 1a of upper 20 bits of address 1 is tag memory with comparison function
Input to 10. This tag memory 10 has a plurality of 17-bit memory units 10a ... 10a to which the upper 17 bits of a 20-bit tag address are input and a plurality of 3 bits to which the lower 3 bits are input.
Bit memory section 10b ... 10b is divided.

Each of the 17-bit memory sections 10a ... 10a is shared by a plurality of entries which are a part of all the entries of the data memory 7. 3-bit memory section 10b ... 10b
Each is provided for each entry of the data memory 7, and is the same as the 17-bit memory unit 9a of FIG. 17-bit memory section 10a ... 10a and 3-bit memory section 10b ... 10
b stores a part of the tag address corresponding to each. The other configuration is the same as the configuration of the cache memory shown in FIG. 1, and the same components are designated by the same reference numerals.

Next, the operation of this cache memory will be described. As a result of decoding the 8-bit entry address 1b by the entry decoder 2 when writing data to the cache memory, the 17-bit memory unit 10a is shared by the corresponding 17-bit memory unit 10a for the specified entry. If there is no valid data stored in the entry, or if the upper 17 bits of tag address 1a
When the contents of the bit memory unit 10a match, data is written in the data memory 7 via the data writing / reading circuit 6, and the lower 3 bits of the tag address 1a are written in the 3-bit memory unit 10b. .

Further, the upper 17 bits of the tag address 1a are written also in the 17-bit memory section 10a which is shared by a plurality of entries which are a part of all the entries. However, if the higher 17 bits of the latter tag address 1a and the contents of the 17-bit memory unit 10a match, the higher 17 bits of the tag address 1a is not necessarily the 17-bit memory unit 10a.
There is no need to write in.

On the contrary, when data is written to the cache memory, the 8-bit entry address 1b is decoded by the entry decoder 2 and, as a result, the tag address 1a in the corresponding 17-bit memory section 10a is corresponding to the designated entry. If the high-order 17 bits of the above do not match the contents of the 17-bit memory unit 10a, and valid data exists in the entry in which the 17-bit memory unit 10a is shared, the data memory No writing at all,
No data is cached.

When data is read from the cache memory, the entry address 1b is decoded by the entry decoder 2 and, as a result, the valid / invalid judgment of the corresponding valid bit 4 and the tag address 1a are performed for the designated entry. The lower 3 bits of the tag and the contents of the 3-bit memory section 10b are compared, and the tag address 1a
If the result of the comparison is valid and the comparison results match, the hit signal generator 5 outputs the hit signal HT.
There is output, data read DT _R from the data memory 7 through the data writing and reading circuit 6 is read out to the outside through the control unit 8.

In this way, the cache memory shown in FIG. 2 has the comparison function tag memory 10 as the 17-bit memory unit 10a.
... 10a and 3-bit memory unit 10b ... 10b, and the 17-bit memory unit 10a is shared by a plurality of entries that are a part of all entries of the data memory 7 The area above can be reduced, and a cache memory with a small area on the tag memory chip can be realized. Further, even data having an address in which the upper 17 bits of the tag address 1a are different can be cached.

FIG. 3 is a block diagram showing the configuration of still another embodiment of the cache memory according to the present invention. The tag address 1a of the upper 20 bits of the address 1 is input to the plurality of tag memory units 12a, 12b ... 12m with comparison function.
Tag memory unit 12a (12b ... 12m) is the tag address
Tag memory with comparison function 11a (11b
... 11m) and valid bits 4a (4b ... 4m) for judging the validity / invalidity of data for all entries in the data memory 7, and the comparison result of the tag address 1a and the contents of the tag memory 11a (11b ... 11m) , A hit signal generator 5a (5b ... 5m) that generates a hit signal HT based on the value of the valid bit 4a (4b ... 4m) of the entry specified by the entry address 1b. The hit signal HT output from the hit signal generation units 5a, 5b ... 5m is input to the hit signal control unit 13 that controls the final hit signal, and the hit signal HT output from the hit signal control unit 13 is 8 is input. The other configuration is the same as the configuration of the cache memory shown in FIG. 1, and the same components are designated by the same reference numerals.

Next, the operation of this cache memory will be described. When valid data is not stored in all entries when writing data to the cache memory, write the 20-bit tag address 1a to the tag memory of the specified tag memory unit and specify it with the entry address 1b. The valid bit of the entry to be set is set to the valid state, and the data is written to the entry designated by the entry address of the data memory 7.

If data is already stored in the data memory 7 and the contents stored in the tag memory match the tag address 1a of the data to be written, the valid data of the tag memory unit is validated. The bit is set to the valid state, and the data is written in the entry designated by the entry address of the data memory 7. Further data memory 7
Data is already stored in the tag memory, the content stored in the tag memory does not match the tag address 1a of the data to be written, and the valid bit is not valid for all entries. If it exists, write the 20-bit tag address 1a for that tag memory unit to the 20-bit tag memory, set the valid bit of the entry specified by the entry address to the valid state, and write the data. Data is written in the entry designated by the entry address of the memory 7.

However, when writing data, as described above, when data is not stored in all the entries in the data memory 7, or when data is already stored in the data memory 7, the tag memory When the content stored in the tag and the tag address of the data to be written match, or the data is already stored in the data memory 7 and the content stored in the tag memory and the tag of the data to be written If the address 1a does not match, and none of the conditions when there is a tag memory unit for which valid bits are not valid for all entries are not satisfied, then no data is written to the data memory, No data is cached.

When reading data from the cache memory, the entry address 1b is set to the entry decoder 2
As a result of decoding in step 1, for the specified entry, the validity / invalidity of the data by the valid bits of each tag memory unit 12a, 12b ... 12m is determined, and the comparison between the tag address 1a and the content of the tag memory is performed and the determination is made. If the result is valid and the tag addresses match, the hit signal HT is output from the hit signal generation unit. Then, the hit signal HT from all the tag memory units 12a, 12b, ...
There If output data DT _R of a given entry which is read via the data writing and reading circuit 6 is read out to the outside through the control unit 8.

As described above, in the cache memory shown in FIG. 3, one tag memory for storing n bits of the tag address from the MPU and a valid bit for judging the validity / invalidity of the data for all entries are used. By providing a plurality of tag memory units, it is possible to realize a function similar to that of the conventional cache memory by using a tag memory having a smaller number of data memory entries, while reducing the area of the tag memory on the chip. As a result, the yield of the cache memory can be improved.

In the present embodiment, the case in which the single tag memory and the single data memory are provided has been described, but the number is not limited to one. That is, the same effect can be obtained even if the tag memory and the data memory are combined into one way and the set associative structure has a plurality of ways. Further, in the present embodiment, the tag memory is divided into a 17-bit memory section and a 3-bit memory section, but this is merely an example and the present invention is not limited to this.

[0038]

As described in detail above, the cache memory of the first invention is a tag memory that stores all of the tag address n bits from the MPU for each data stored in the data memory. Of the a-bit memory unit for storing the upper-order a bits and the lower-b-bit memory unit for storing the lower-order b bits, and the a-bit memory unit is shared by all the entries of the data memory Therefore, a cache memory in which the area of the tag memory on the chip is reduced can be realized, and as a result, the yield of the cache memory can be improved.

The cache memory according to the second aspect of the present invention comprises a tag memory unit comprising one tag memory for storing a tag address of n bits and a valid bit for judging validity / invalidity of data for all entries of the data memory. Since multiple tags are provided, if the tag address n bits match,
It becomes possible to cache data for a given entry, and it is possible to use a number of tag memories less than or equal to the number of entries of the data memory, and it is possible to realize a cache memory in which the area of the tag memory on the chip is reduced. The yield of the cache memory can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a cache memory according to the present invention.

FIG. 2 is a block diagram showing a configuration of another embodiment of a main part of a cache memory according to the present invention.

FIG. 3 is a block diagram showing a configuration of still another embodiment of the main part of the cache memory according to the present invention.

FIG. 4 is a block diagram showing a configuration of a main part of a conventional cache memory.

[Explanation of symbols]

2 entry decoder, 4 valid bits, 4a, 4b ~
4m valid bit, 5 hit signal generator, 7 data memory, 9 tag memory, 9a 17 bit memory,
9b 3-bit memory, 10 tag memory, 10a, 10a ...
17-bit memory section, 10b, 10b ... 3-bit memory section, 11
a, 11b to 11m 20-bit memory unit, 12a, 12b to 12m Tag memory unit.

Claims (3)

[Claims] 1. The used data is stored in a data memory for an entry designated by an entry address which is a part of the address, and n is a part of the stored address.
The tag address of the bit is stored in the tag memory, and later,
In the cache memory in which the data from the data memory is read when the same tag address as that stored in the tag memory for the entry specified by the address is input to the tag memory, , A tag address n bits are divided into an a-bit memory unit for storing high-order a bits and a b-bit memory unit for storing low-order b bits (a + b = n, a, b, and c are integers). A cache memory characterized in that a single bit memory unit is provided commonly to all entries of the data memory. 2. The cache memory according to claim 1, wherein the a-bit memory section is provided commonly to a plurality of entries which are a part of all the entries of the data memory. 3. The used data is stored in a data memory, the n-bit tag address of the stored data is stored in the tag memory, and the tag address stored in the tag memory is the same as the tag address. A tag memory for storing n bits of the tag address in a cache memory from which data is read from the data memory when input to
A cache memory comprising a plurality of tag memory units each having a valid bit for determining whether data of all entries of the data memory is valid or invalid.