JPH04324194A - Rom circuit - Google Patents

Abstract

PURPOSE:To enable quick access even for a ROM with a large capacity and to prevent from reducing the performance of a computer system. CONSTITUTION:Data is temporarily stored by a cache memory 2. The cache memory 2 and an electrically erasable and programmable ROM 5 are selected by a multiplexer 1 and the data is outputted. The address of data read out of the electrically erasable and programmable ROM 5 and stored in the cache memory 2 is stored in a cache memory/address storing section 3. An address from a central processing unit and the address in the cache memory/address storing section 3 are compared by an address comparator 4 and when the address outputted from the central processing unit is coincident with the address stored in the cache memory/address storing section 3, a storing place selection specifying signal is outputted to the multiplexer 1 so as to read and output the data stored in the cache memory 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ROM circuit, and more particularly to a ROM circuit with a cache.

0002

2. Description of the Related Art Conventional ROM circuits are slower than memories such as SRAMs, and when accessed by a CPU, the CPU accesses the memory in accordance with the access speed of the ROM.

0003

[Problem to be solved by the invention] The above-mentioned conventional ROM
When the circuit is accessed by the CPU, the CPU's memory access is matched to the access speed of the ROM, which has the drawback of reducing the performance of the computer system.

An object of the present invention is to provide a ROM circuit that allows high-speed access even to a large-capacity ROM and prevents a decrease in computer system performance.

[0005]

[Means for Solving the Problems] The ROM circuit of the present invention includes:
A ROM that includes a ROM and is accessed by a central processing unit.
In the circuit, (A) a cache memory that temporarily stores data in the ROM and is faster than the ROM; (B)
) a multiplexer that receives a storage location selection instruction signal, selects the cache memory and the ROM according to the storage location selection instruction signal, and outputs the data;
(D) a cache memory address storage unit storing addresses of data read from the ROM and stored in the cache memory; (D) an address output from the central processing unit and an address stored in the cache memory address storage unit; and when the address output from the central processing unit matches the address of the data stored in the cache memory address storage section, the data stored in the cache memory is read and output. an address comparator that outputs the memory location selection instruction signal to the multiplexer;
It is configured with.

[0006]

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a ROM circuit according to the present invention.

The ROM circuit of this embodiment shown in FIG. 1 includes an electrically erasable programmable ROM 5, a cache memory 2 which temporarily stores data in the electrically erasable programmable ROM 5, and which is faster than the electrically erasable programmable ROM 5; A multiplexer 1 that receives a storage location selection instruction signal, selects the cache memory 2 and the electrically erasable programmable ROM 5 in accordance with the storage location selection instruction signal, and outputs the data; and an electrically erasable programmable RO.
A cache memory address storage section 3 stores the address of data read out from inside the M5 and stored in the cache memory 2, and an address output from the central processing unit and an address stored in the cache memory address storage section 3 are stored. When the address output from the central processing unit matches the address stored in the cache memory address storage section 3, the multiplexer 1 is instructed to read and output the data stored in the cache memory 2. It consists of an address comparator 4 that outputs a selection instruction signal.

Next, the operation will be explained.

In FIG. 1, the cache memory 2 includes:
Part of the data in the electrically erasable programmable ROM 5, frequently accessed data, is temporarily stored.

Here, if an address signal sent from the central processing unit (not shown) for accessing data in the electrically erasable programmable ROM 5 is received from the address bus 7, the address comparator 4
compares the address output from the central processing unit and the address stored in the cache memory address storage unit 3, and determines whether the address output from the central processing unit is the address stored in the cache memory address storage unit 3. When they match, a storage location selection instruction signal 9 is output to the multiplexer 1 so that the data stored in the cache memory 2 is read out and output. Furthermore, when the address output from the central processing unit does not match the address stored in the cache memory address storage section 3,
A memory location selection instruction signal 9 is output to the multiplexer 1 so as to read and output data from the electrically erasable programmable ROM 5.

The multiplexer 1 receives a memory location selection instruction signal 9 from the address comparator 4, selects either the cache memory 2 or the electrically erasable programmable ROM 5 in accordance with the memory location selection instruction signal 9, and selects the selected one. Data is read out by address and output. The data selected and output by the multiplexer 1 is sent to the central processing unit via the data bus 6.

Further, the address comparator 4 outputs a memory location selection instruction signal 9 to the multiplexer 1, and at the same time, when data is read from the cache memory 2, the address comparator 4 compares when data is read from the electrically erasable programmable ROM 5. Since the access time is short, an access time notification signal 8 is sent to the central processing unit to notify the central processing unit that the access time is short.

Note that when there is no data to be accessed from the central processing unit, the cache memory address storage section 3 discards the least used data and stores newly accessed data from the electrically erasable programmable ROM 5. It is read out and stored in the cache memory 2.

As described above, by providing the cache memory section inside the ROM circuit, even a large-capacity ROM can be accessed at high speed, and it is possible to prevent the performance of the computer system from deteriorating.

[0016]

As explained above, the ROM circuit of the present invention can perform high-speed access even with a large capacity ROM by providing a cache memory section inside the ROM circuit, thereby improving the performance of the computer system. This has the effect of preventing the decline.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a ROM circuit of the present invention.

[Explanation of symbols]

1 Multiplexer 2 Cache memory 3 Cache memory address storage section 4
Address comparator 5 Electrically erasable programmable ROM (EEP)
ROM) 6 Data bus 7 Address bus 8 Access time report signal 9 Memory location selection instruction signal

Claims (2)

[Claims] 1. A ROM circuit that includes a ROM and is accessed by a central processing unit, comprising: (A) a cache memory that temporarily stores data in the ROM and is faster than the ROM; (B) a storage location selection instruction signal. (C) a multiplexer that selects the cache memory and the ROM according to the storage location selection instruction signal and outputs the data; (C) a multiplexer that receives the address of the data read from the ROM and stored in the cache memory; (D) compares the address output from the central processing unit with the address stored in the cache memory address storage unit, and compares the address output from the central processing unit with the address stored in the cache memory address storage unit; an address comparator that outputs the memory location selection instruction signal to the multiplexer so as to read and output the data stored in the cache memory when the address matches the address of the data stored in the cache memory address storage unit; A ROM circuit characterized by comprising: 2. The ROM circuit according to claim 1,
A ROM circuit characterized in that the ROM is an electrically erasable programmable ROM.