JPS605021B2 - buffer memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a buffer memory device in a data processing device.

Generally, when trying to register new data in a buffer consisting of a storage area in units of multiple blocks, one of the data previously stored in the buffer must be removed as a replacement target. do not have.

At this time, as a method for determining which data to flush out, one method is to randomly determine one of the buffers without any regularity and flush it out, and another method is generally to use FIF○ (FirstlnFirstOut).
) method, in which the first registered data is purged.

Furthermore, as another method, LRU (Least Rec
There is a method called the entryUsed) method, in which the data in the buffer is referenced,
A method is used to delete data that has not been used for the longest time. The LRU method is most effective since even if data is registered in the buffer but has not been used for a long time, there is a low probability that it will be used in the future. On the other hand, in a data processing device, a read/write memory is used as a means to improve its performance, and a cache memory that holds a copy of data in the main memory or a conversion table between virtual addresses and real addresses in a virtual memory computer is used. A TLB (Trans
However, when these buffer memories adopt the LRU method as the eviction control method, they have an LRU memory that stores LRU control bits, and the data on the buffer memory When referring to LR
The storage location of the referenced data in the U memory is set to have the highest priority, and when attempting to register new data in the buffer memo, it is set to the storage location of the referenced data in the LRU memory with the lowest priority, i.e. , determines the data location that has not been referenced for the longest time, and purges that data.

Furthermore, in a multiprocessor system consisting of multiple central processing units, for example, in a cache memory, when one central processing unit rewrites data on the main memory, that data is stored in the cache memory of the other central processing unit. If the data is registered, it is necessary to change the data to new data or to invalidate the data in the cache memory.

This process generally involves providing communication means for transmitting main memory addresses between each central processing unit, and when a central processing unit performs write access to the main memory, it transmits the address to another central processing unit, and The central processing unit that receives the address checks the cache memory and, if the block data at that address is registered, resets the valid bit indicating the validity of the block.

At this time, an empty block in which no data is registered will be created on the cache memory. When trying to register new data in this cache memory, LRU
Instead of deciding which blocks should be evicted based only on the memory contents, we first check the status of the valid bits, and if there is an empty block with no data registered, we can preferentially register data in that block. It will be advantageous.

Therefore, the logic for determining the position of a block to be evicted is to first check whether there is an empty block based on the state of the valid bit, and if there is an empty block, it will be allocated preferentially to that block, and if there is no empty block, then L
It is necessary to examine the contents of the RU memory and evict the block with the lowest priority based on the contents.
This method has the drawback of complicating the logic for determining eviction and increasing the amount of hardware needed to implement it.

An object of the present invention is to eliminate the above drawbacks by rewriting the contents of the LRU memory so that when data on a certain block is invalidated, the valid bit is reset and the invalidated block has the lowest priority. When determining the block to be solved and evicted, LRU realizes the same function as before using only the contents of LRU memory with less hardware.
An object of the present invention is to provide a buffer memory device using the RU method.

According to the present invention, there is provided a data storage means for storing data having a storage area in units of blocks, and valid information indicating a case where data is stored in the data storage means corresponding to each block of the data storage means. effective information storage means for storing, priority order instruction information storage means for storing priority order instruction information indicating the priority order of the block unit corresponding to the storage position of the data storage means, and the data storage means when the data is accessed. updating means for updating the contents of the priority order instruction information storage means so that the priority order instruction information corresponding to the accessed storage block in the means is given the highest priority; and any valid information in the valid information storage means. and updating means for updating the contents of the priority order instruction information storage means so that the priority order instruction information of the storage block corresponding to the valid information reset at the time of the reset is set to the lowest priority; In order to replace the data stored in the data storage means with other data, a storage block whose data should be replaced with the lowest priority storage block based only on the priority order instruction information stored in the priority order instruction information storage means. A buffer memory device characterized in that it is provided with means for determining .

Next, the present invention will be explained in detail with reference to the drawings.

First, regarding the replacement algorithm IJ system used in the present invention, a case of a buffer consisting of four blocks will be explained.

Memory 1 in FIG. 1 is a data storage memory having 256×4 blocks, and memory 2 has 6 LRU control bits for each of the 256 words (i.e. priority instruction information indicating the priority of each block). ). The LRU control bit is a bit that indicates the temporal relationship in which the data within each block is accessed.
For a certain control bit lij (where i and i represent block numbers), when control bit lij = logic 1'', it indicates that the data in block i was accessed after the data in block i. , control bit lij=logic "0" indicates that the data in block i was accessed earlier than the data in block i.

These 6 LRU control bits, lo,, lo2, 3, 1, 2, 1, 3, and 1, can represent the referenced order of the 4 blocks, making it possible to express one block more than another. indicates that it was also accessed later,
That is, a method of rewriting a block to indicate the highest priority and a method of rewriting a block to indicate the lowest priority will be explained with reference to FIG.

In Figure 2, to set a block among the four blocks to have the highest priority, set the bit in the row direction of that block number to logic "1" and the bit in the column direction to logic "1". This can be achieved by rewriting the value to 0''.

For example, to set block 1 to the highest priority, set row bits 1, 2 and 1, 3 to logic "1".
Rewrite the bit L in the column direction to logic 0''.On the contrary,
To set a certain block to have the lowest priority, contrary to the above, rewrite the bits in the row direction of the block number to logic "0" and the bits in the column direction to logic "1". realizable.

For each block, the LRU to be updated when setting the block to the highest rank and when setting it to the lowest rank.
The relationship between the control bits is shown below.

Next, when new data is registered in this buffer, the data in one of the four blocks must be evicted, but the logic that detects the block with the highest priority for evicting, that is, the block with the lowest priority. The formula is shown below. Flock 0=L.・1 of 1.

3 Block 1=L.・18・1,3 Flock 2=shi2・1,2・123 Flock 3 = L3・1, 3.123 FIG. 3 is a diagram showing an embodiment of the present invention.

This embodiment shows a four-level set-associative cache memo system. In Figure 3,
The memory 32 is a data storage memory that stores data on the main storage device 6 in blocks, and has entries of 256 sets x 4 conversions. The memory 4 stores, corresponding to each entry in the memory 32, a valid bit indicating the validity of the block data (that is, whether the block data is stored in the memory 32) and an address on the main memory of the block data. When the valid bit is logic ul'', it indicates that data is stored in the corresponding block of the data storage memory 32.The memory 23 has four memory blocks corresponding to each set of the memories 14 and 32. 6-bit LR indicating priority between blocks of
This is a memory that stores U bits. Access to the cache memory from the central processing unit 4 is performed using address information via path 1001 and write data via path 101 in the case of write access.

The access operation from the central processing unit 4 will be explained.
For discussion access from central processing unit 4, pass 10
The address information on 0 is set in the register 10', its lower bit 202 is selected by the selection circuit 12, and given as the address of the memory 14 by the path 205,
The memory 14 is proposed. Valid bits and address information for each of the four blocks read from memory 14 are input to comparison circuits 15, 16, 17 and 18 via paths 210, 211, 212 and 213. The upper bit of register 10 is passed to the other input of each comparison circuit.
1, and both data are compared. The valid bit of the proposal data from memo IJ14 is logical 1''
, and when the address information and the contents of the path 201 are equal, it means that the data accessed from the central processing unit 4 is stored in that block (referred to as a cache hit), and the outputs 214 to 214 of the comparison circuit The corresponding signal of 217 becomes logic 1''.

When all comparison circuits cannot find the above-mentioned match (referred to as a cache miss), it indicates that the target data is not stored in the memory 32, and a read access to the main memory 6 is performed.

Access to the memory 32 is performed in parallel with the above operation using the address of the /path 202, and the output data of each block is input to the selection circuit 33 via paths 232-235. In case of cache hit, paths 214-217
The data is selected by the selection circuit 19 and stored in the register 20.
At the same time, the selection circuit 33 selects path 2.
The hit block data is selected from among the data 32 to 235 and set in the register 34 through path 236.

The data in register 34 is sent to central processing unit 4 via path 102. In the case of a cache hit, in the 4-bit register 20', only the bit for the hit block is set to logic 1'', and the other bits are set to logic 0'', and the most recent reference to the hit block is set. The LRU bit of the memory 23 is updated so that it has the highest priority to indicate that it has been updated. Therefore, in the LRU memory control circuit 22, the register 20
According to the algorithm described above, the block with logic 1" is given the highest priority according to the contents of the memory 23.
write data is generated and written to the address location of the memory 23 indicated by the address information of the register 21.

When a cache hit occurs due to a read access from the central processing unit 4, the block referenced by the above operation is always used.

set the highest priority. In the case of a cache mishit, the address information in the register 10 is selected by the selection circuit 35 and sent to the main memory device 6 via the register 36, thereby making a proposed access to the main memory device.

When the input data from the main storage device 6 is sent via the bus 105 by this access, it is selected by the selection circuit 30 and set in the register 31, and
is set in the register 34 via the selection circuit 33 and sent to the central processing unit 4 via the path 102.

The meeting data from the main storage device 6 is sent to the central processing unit 4 and also stored in the memory 32. At this time, data is stored in the block having the lowest priority according to the LRU bit in the memory 23 among the four blocks, that is, the most previously referenced block position. Address register 10 for access request from central processing unit 4
The LRU bit of the memory 23 held in the register 21 and read by the address on the path 225 is set in the register 24, and based on its contents, the eviction block detection circuit 25 determines the block with the lowest priority. In the output of the expelled block detection circuit, only the bit corresponding to the next block position is set to logic "1", and the register 2 is set via the selection circuit 19 by the path 224. The contents of register 20 are transferred to memory 14, memory 32 and LRU memory control circuit 22 by path 220.
The data is input to the memory and used for update processing of each memory.
First, in the memory 32, the output data from the main storage device 6 of the register 31 is written to the block indicated by the address of the path 202 and the block position information of the path 220.

In the memory 14, upper address information of the path 201 is written to the block indicated by the address of the path 205 and the path 220, and logic "1" is written to the valid bit.

As for the memory 23, in order to set the block in which the above data is registered to have the highest priority, the LRU memory control circuit 22 generates setting data and stores it in the memory 23, as in the case of a cache hit. Write.

As shown above, for access from the central processing unit 4, the LRU bit priority for the most recently referenced block in the cache memory is set to the highest priority, and when new data is registered, the LRU bit is given the highest priority. New data is registered by expelling data from blocks with low levels.

Next, the operation in response to a request from the block invalidation control section 5 will be described.

The block invalidation control unit 5 has the same structure as the memory 14,
It has a memory that stores a copy of its contents, and both memories are controlled so that the contents always match.

In addition, the block invalidation control unit 5 receives the main memory address sent when another central processing unit making up the multiprocessor performs write access to the main memory 6, searches the memory within the control unit 5, and searches the memory in the control unit 5, , if the block indicated by the main memory address is registered, a request to invalidate the block is sent to the buffer memory device 3 via path 103. The operation of the flock invalidation control unit 5 is omitted because it has no relation to the present invention.

The path 103 includes address information indicating the block position to be invalidated and 4-bit data in which only the bit corresponding to the block position is logical 1'', and is set in the register 11.

Address information section 303 of register 11 is selected by selection circuit j2 and specifies the address of memory 14 through path 205, and is set in register 21 and specifies the address of memory 23 through path 225. The block position information is input to the valid bit control circuit 13 via a path 204 and set in the register 201 via the selection circuit 19. In the memory 14, the control circuit 13 generates logic ``0'' data as input data for the block position of logic 1'' of the path 204, and by performing a write process, resets the valid bit of the specified block position. do. In the LRU memory control circuit 22, the data for setting the block at the bit position 1'' to the lowest priority is generated according to the contents of the register 20, and the memory 23 is updated. Process.

A block whose data has become invalid due to this process, that is, a block in which no data is registered, has the lowest priority compared to other blocks, and when data from the main storage device 6 is registered by access from the central processing unit. In this case, empty blocks with no data registered will be used preferentially.

Next, the update operation of the memory 23 by the LRU memory control circuit 22 and the configuration of the evicted block detection circuit 25 will be described in the fourth section.
This will be explained with reference to the figures. In Figure 4, memory 2
3 is a memory cell 2301, 2302, 2303, 2312, 231 that can perform a write operation for each LRU bit.
3 and 2323, each memory cell is LR
U bits lo,, lo2, lo3, 1, 2, 1, 3 and 123 are stored respectively. Each memory cell receives address information on a path 225, a write control signal on a path 2216, and an input data signal 221x input for each memory cell.
1 (x=0 to 5) and a write enable signal 221x2. For example, regarding the memory cell 2301, if the write control signal 2216 is a logic 1'' and the write enable signal 22102 is a logic 1'', the contents of the input data signal 22101 are written to the address position of the path 225.

The write control signal 2216 is generated at the timing when either the write signal L22601 or the write signal date 22602 becomes a logic 1", and the write pulse 22603 becomes a logic 1".

Signal L22601 is a control signal that specifies that the block position indicated by the first register 20 is set to the lowest priority, and is generated in response to a request from the block invalidation control unit 5. This is a control signal that designates setting to have the highest priority and is generated by access from the central processing unit 4. In register 2, only the bit for the block whose priority is to be changed is set to a block designation bit of logic 1", and when the write control signal 2216 becomes logic 1" by signal L22601 or signal date 22602. , gate 22×1 (×=0 to 5) depending on the contents of register 20
The input data and write valid signal are determined in the 22.times.2 section, and the corresponding write operation is performed.

Now looking at the write operation using the signal L22601, if the contents of the register 20 at this time are "0100",
Output 221 of gates 2202, 2232 and 2242
02, 22132, and 22142 become logic 1'', and a write operation is performed on memory cells 2301, 2312, and 2313.

At this time, the input data of each memory cell is input to the gate 2201.
, 2231 and 2241 are exclusive ORed with the signal L22601, so the negative logic of the data from 20 becomes input data to each memory cell.

That is, the signal 22101 becomes logic 1'', and the signal 2213
1 and 22141 become logic 0'' and memory cell 2301
, 2312 and 2313 have logic 1'', ``0'', 0
” is written respectively, and this pattern is as shown above.
Block 1 is set to have the lowest priority.

If the register 20 specifies another block, in the same way as above, that block is assigned the LRU so that it has the lowest priority.
Performs memory write operation.

Next, in the case of a write operation using the write signal date 22602, the gate for generating the write valid signal operates in the same manner as above,
The gate 22x1 for generating input data has its input 2260.
Since 1 is logic 0'', the input state of register 20 becomes the input data of each memory cell as it is.Register 2
If the content of 0 is 0100'' as described above, the input data of memory cells 2301, 2312, and 2313 will be 011'', and the block is set to have the highest priority as described above.

As shown in FIG. 4, the configuration of the eviction block detection circuit 25 is very simple, consisting only of the contents of the register 24. In FIG. 4, when the signal 2240 is logic ``1'', block 0 is activated, and when the signal 2241 is logic ``1'', block 0 is activated.
When signal 2242 is logic 1'', block 2
When 243 is logic "1", it indicates that block 3 is the block to be evicted.

As shown above, the circuit for setting a certain block to have the highest priority and the circuit for detecting the block with the lowest priority as an evicted block are very simple and require only a small amount of hardware. This can be achieved by

Although the case of a cache memory is shown in this embodiment, the present invention can be easily applied to buffer memory control to which an LRU calendar change algorithm is applied in a buffer memory such as a TLB.

As explained above, when block data is invalidated, the present invention is configured to set the priority instruction information (LRU bit) to the lowest priority for the block position, so that when registering new data, This has the effect that the means for determining the eviction block can be realized very simply and with less hardware.

[Brief explanation of the drawing]

FIG. 1 shows a four-level buffer memory and the corresponding LRU memory, FIG. 2 shows a matrix of LRU bits for a buffer consisting of four blocks, and FIG. 3 shows an embodiment of the present invention. A block diagram showing the configuration of the cache memory, FIG. 4 is the LRU memory 2 in FIG. 3.
3 is a diagram showing a detailed configuration of the LRU memory control circuit 22 and the eviction block detection circuit 25. FIG. In FIGS. 1 to 4, 1...buffer memory, 2
...LRU memory, 3 ...Buffer memory device, 4
... Central processing unit, 5 ... Flock invalidation control section, 6 ... Main storage device, 10, 11,
20, 21, 24, 31, 34... register, 32. ．．
・．． ．．・Cache memory, 14...Address, memory for storing valid bits, 23...LRU memory, 1
3... Valid bit control circuit, 12, 19, 30
, 33, 35... Selection circuit, 15, 16, 17
, 18... Comparison circuit, 22... LRU memory control circuit,
25... Evicted block detection circuit, 2201, 2
202, 2211, 2212, 2221, 2222, 2
231, 2232, 2241, 2242, 2251, 2
252, 2261, 2262, 250, 251, 252
,253...Logic gate, 2301,2302,2
303, 2312, 2313, 2323...memory cell, 100, 101, 103-105, 200-206,
210-218, 220-225, 230-236, 2
40,2200-2203,221×1 (x=0-5)
,221×2,22600~22603,2216,2
220-2225, 2230-2235, 2240-2
243... Connection line. Figure 1 Figure 2 Figure 3 Figure Salmon

Claims (1)

[Claims] 1. A data storage means for storing data having a storage area in blocks, and a valid information storage for storing valid information indicating when data is stored in the data storage means corresponding to each block of the data storage means. means, priority order instruction information storage means for storing priority order instruction information indicating the priority order of the block unit corresponding to the storage location of the data storage means; updating means for updating the contents of the priority order instruction information storage means so that the priority order instruction information corresponding to the stored memory block is given the highest priority; and means for resetting any valid information in the valid information storage means. , updating means for updating the contents of the priority order instruction information storage means so that the priority order instruction information of the storage block corresponding to the valid information reset at the time of the reset is set to the lowest priority; means for determining the lowest priority storage block as the storage block whose data is to be replaced, based only on the priority order instruction information stored in the priority order instruction information storage means, in order to replace the stored data with other data; A buffer memory device comprising: