JPS57132229A - Direct memory access controller - Google Patents

Direct memory access controller

Info

Publication number
JPS57132229A
JPS57132229A JP1790881A JP1790881A JPS57132229A JP S57132229 A JPS57132229 A JP S57132229A JP 1790881 A JP1790881 A JP 1790881A JP 1790881 A JP1790881 A JP 1790881A JP S57132229 A JPS57132229 A JP S57132229A
Authority
JP
Japan
Prior art keywords
data
memory
output
processing
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1790881A
Other languages
Japanese (ja)
Inventor
Masatoshi Kameyama
Hitoshi Ito
Yoshihiko Sakashita
Osamu Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1790881A priority Critical patent/JPS57132229A/en
Publication of JPS57132229A publication Critical patent/JPS57132229A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To speed data processing by providing an arithmetic logical circuit, by successively processing a large amount of data in a memory at a high speed, and by writing the results in different addresses or original addresses. CONSTITUTION:A source address counter 14 holds the destination address of input data to be read in a memory, and a destination address counter 18 holds the destination address of output data to be written. The memory is accessed by the output of a counter 14 to read the data out of the memory and to input it to a source data register 27, whose output is inputted to an arithemtic logical circuit 33, thereby performing arithmetic specified by the output of an arithmetic control register 37. Consequently, counters 14 and 18 go up by one every time the processing of one data ends and at the same time, a data counter 40 goes down by one, thereby starting processing of the next data.
JP1790881A 1981-02-09 1981-02-09 Direct memory access controller Pending JPS57132229A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1790881A JPS57132229A (en) 1981-02-09 1981-02-09 Direct memory access controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1790881A JPS57132229A (en) 1981-02-09 1981-02-09 Direct memory access controller

Publications (1)

Publication Number Publication Date
JPS57132229A true JPS57132229A (en) 1982-08-16

Family

ID=11956842

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1790881A Pending JPS57132229A (en) 1981-02-09 1981-02-09 Direct memory access controller

Country Status (1)

Country Link
JP (1) JPS57132229A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03505016A (en) * 1989-03-15 1991-10-31 エイエスティー・リサーチ，インコーポレイテッド Controller for direct memory access
JPWO2008068937A1 (en) * 2006-12-01 2010-03-18 三菱電機株式会社 Data transfer control device and computer system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587359A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Information transfer device
JPS55135930A (en) * 1979-04-11 1980-10-23 Toshiba Corp Data transfer system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5587359A (en) * 1978-12-25 1980-07-02 Fujitsu Ltd Information transfer device
JPS55135930A (en) * 1979-04-11 1980-10-23 Toshiba Corp Data transfer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03505016A (en) * 1989-03-15 1991-10-31 エイエスティー・リサーチ，インコーポレイテッド Controller for direct memory access
JPWO2008068937A1 (en) * 2006-12-01 2010-03-18 三菱電機株式会社 Data transfer control device and computer system
US8127052B2 (en) 2006-12-01 2012-02-28 Mitsubishi Electric Corporation Data transfer control device and computer system

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