JPS57136278A - Convolutional arithmetic circuit - Google Patents
Convolutional arithmetic circuitInfo
- Publication number
- JPS57136278A JPS57136278A JP2243481A JP2243481A JPS57136278A JP S57136278 A JPS57136278 A JP S57136278A JP 2243481 A JP2243481 A JP 2243481A JP 2243481 A JP2243481 A JP 2243481A JP S57136278 A JPS57136278 A JP S57136278A
- Authority
- JP
- Japan
- Prior art keywords
- delay time
- series
- written
- data
- prescribed delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/15—Correlation function computation including computation of convolution operations
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To simplify the circuit constitution and decrease the processing time, by giving an operation to a storage device to which the impulse response having a prescribed delay time is successively written and another storage device to which the input signal that varies with every prescribed delay time is successively written. CONSTITUTION:The storage devices HP and XP consisting of RAMs which are capable of reading and writing are provided, and a data Da of an inpulse response series of each delay time is written into the device HP with a series of circulating memory addresses. At the same time, each data Da of the input signal series which varies with a prescribed delay time is written in turn into the device XP through one of a series of circulating memory addresses and for each delay time. Furthermore the reading address of the device XP is designated and preset to a presetable counter C2 which is preset in the writing order of the device XP. In addition to this counter C2, a multiplier/adder M is provided to fetch and calculate the data which are successively read out of both devices HP and XP with every prescribed delay time. In such way, the circuit constitution is simplified.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2243481A JPS57136278A (en) | 1981-02-17 | 1981-02-17 | Convolutional arithmetic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2243481A JPS57136278A (en) | 1981-02-17 | 1981-02-17 | Convolutional arithmetic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS57136278A true JPS57136278A (en) | 1982-08-23 |
Family
ID=12082580
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2243481A Pending JPS57136278A (en) | 1981-02-17 | 1981-02-17 | Convolutional arithmetic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS57136278A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60168269A (en) * | 1984-02-13 | 1985-08-31 | Toshiba Corp | Convolutional arithmetic circuit |
-
1981
- 1981-02-17 JP JP2243481A patent/JPS57136278A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60168269A (en) * | 1984-02-13 | 1985-08-31 | Toshiba Corp | Convolutional arithmetic circuit |
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