JPS5719860A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5719860A
JPS5719860A JP9293880A JP9293880A JPS5719860A JP S5719860 A JPS5719860 A JP S5719860A JP 9293880 A JP9293880 A JP 9293880A JP 9293880 A JP9293880 A JP 9293880A JP S5719860 A JPS5719860 A JP S5719860A
Authority
JP
Japan
Prior art keywords
access
gates
actual address
memory
memory control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9293880A
Other languages
Japanese (ja)
Other versions
JPS6047629B2 (en
Inventor
Kazuo Tajiri
Shizuo Shiokawa
Yoshimi Fukumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP55092938A priority Critical patent/JPS6047629B2/en
Publication of JPS5719860A publication Critical patent/JPS5719860A/en
Publication of JPS6047629B2 publication Critical patent/JPS6047629B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0607—Interleaved addressing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To elevate a processing capacity and also to get rid of an error of a readout information, by executing an access processing in paralle, when an actual address space which has been made multiple by plural memory units has been accessed simultaneously from plural memory control parts. CONSTITUTION:In case of a readout access to an actual address space 12, if memory control parts MCU 5,6 do not access a memory unit 7, only an AND gate 20 outputs ''1'', and selects and accesses the unit 7. In case of a write-in access to an actual address belonging to the space 12, since outputs of NAND gates 23-25 and OR gates 31, 32 are all ''1'', when AND gates 17-19 are ''1'', the respective corresponding gates 20-22 become ''1'' immediately. Therefore, write-in access can be executed simultaneously to all the memory units that are not accessed from other control part MCU, among memory units 7-9.
JP55092938A 1980-07-07 1980-07-07 Memory control method Expired JPS6047629B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55092938A JPS6047629B2 (en) 1980-07-07 1980-07-07 Memory control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55092938A JPS6047629B2 (en) 1980-07-07 1980-07-07 Memory control method

Publications (2)

Publication Number Publication Date
JPS5719860A true JPS5719860A (en) 1982-02-02
JPS6047629B2 JPS6047629B2 (en) 1985-10-22

Family

ID=14068414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55092938A Expired JPS6047629B2 (en) 1980-07-07 1980-07-07 Memory control method

Country Status (1)

Country Link
JP (1) JPS6047629B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5786962A (en) * 1980-11-19 1982-05-31 Hitachi Ltd Memory control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5786962A (en) * 1980-11-19 1982-05-31 Hitachi Ltd Memory control system

Also Published As

Publication number Publication date
JPS6047629B2 (en) 1985-10-22

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