JPS5786962A - Memory control system - Google Patents

Memory control system

Info

Publication number
JPS5786962A
JPS5786962A JP55161936A JP16193680A JPS5786962A JP S5786962 A JPS5786962 A JP S5786962A JP 55161936 A JP55161936 A JP 55161936A JP 16193680 A JP16193680 A JP 16193680A JP S5786962 A JPS5786962 A JP S5786962A
Authority
JP
Japan
Prior art keywords
signal
selection
turned
write
memory controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55161936A
Other languages
Japanese (ja)
Inventor
Yoshihiro Miyazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP55161936A priority Critical patent/JPS5786962A/en
Publication of JPS5786962A publication Critical patent/JPS5786962A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To perform the reading operations of many processors simultaneously and to increase a total processing speed by accepting a write request according to the selection of a memory controller, which has the right of selection, among multiple memory controllers and by selecting a readout request by each device individually. CONSTITUTION:Write and read request signals 12 and 13 from processors are inputted to write and readout request temporary storage circuits 14 and 15 of common memory controllers 11 and 11' and a processor's number having top priority is outputted through an encoder 5. This coded selection signal 6 is outputted to the other memory controller through an interface and also inputted to a selector 7, which receives a coded selection signal 6' from the other control memory controller at its opposite-side input. When a signal 8 having the right of selection is turned on or when a signal 19 indicating that there is a write request is turned off, the signal 6 of the device is selected by the selector 7 and when the signal 8 is turned off and the signal 19 is turned on, the signal 6' of the other device is selected, thereby returning a selection signal 10 to each processor through a decoder 9.
JP55161936A 1980-11-19 1980-11-19 Memory control system Pending JPS5786962A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55161936A JPS5786962A (en) 1980-11-19 1980-11-19 Memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55161936A JPS5786962A (en) 1980-11-19 1980-11-19 Memory control system

Publications (1)

Publication Number Publication Date
JPS5786962A true JPS5786962A (en) 1982-05-31

Family

ID=15744846

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55161936A Pending JPS5786962A (en) 1980-11-19 1980-11-19 Memory control system

Country Status (1)

Country Link
JP (1) JPS5786962A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118159A (en) * 1980-02-22 1981-09-17 Hideo Aiiso Common storage device
JPS5719860A (en) * 1980-07-07 1982-02-02 Nippon Telegr & Teleph Corp <Ntt> Memory control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56118159A (en) * 1980-02-22 1981-09-17 Hideo Aiiso Common storage device
JPS5719860A (en) * 1980-07-07 1982-02-02 Nippon Telegr & Teleph Corp <Ntt> Memory control system

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