JPS6481031A - Data control system - Google Patents

Data control system

Info

Publication number
JPS6481031A
JPS6481031A JP23840387A JP23840387A JPS6481031A JP S6481031 A JPS6481031 A JP S6481031A JP 23840387 A JP23840387 A JP 23840387A JP 23840387 A JP23840387 A JP 23840387A JP S6481031 A JPS6481031 A JP S6481031A
Authority
JP
Japan
Prior art keywords
write
register
data
read
addresses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23840387A
Other languages
Japanese (ja)
Inventor
Isao Karasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23840387A priority Critical patent/JPS6481031A/en
Publication of JPS6481031A publication Critical patent/JPS6481031A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To shorten an access time by performing comparison between the write and read addresses of a memory designated by a horizontal microprogram and transferring data directly to a read data storing means from a write data storing means with no writing action carried out only when the coincidence is obtained between said two addresses. CONSTITUTION:The contents of the write and read address designating field 7 and 8 of a microinstruction register 6 and stored in the write and read address registers 9 and 10 respectively. Then the write and read addresses are compared with each other by a comparison/decision circuit 6. When the coincidence is obtained between both addresses, the decision output signal of a line 12 becomes active. Receiving this active signal, a gate circuit 14 controls a data bus 13 so that the connection is secured between a write data register 1 and a read data register 5. Then the data on the register 1 is stored directly into the register 5 with no intervention of a memory 2.
JP23840387A 1987-09-22 1987-09-22 Data control system Pending JPS6481031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23840387A JPS6481031A (en) 1987-09-22 1987-09-22 Data control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23840387A JPS6481031A (en) 1987-09-22 1987-09-22 Data control system

Publications (1)

Publication Number Publication Date
JPS6481031A true JPS6481031A (en) 1989-03-27

Family

ID=17029683

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23840387A Pending JPS6481031A (en) 1987-09-22 1987-09-22 Data control system

Country Status (1)

Country Link
JP (1) JPS6481031A (en)

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