JPS57123580A - Buffer storage device - Google Patents
Buffer storage deviceInfo
- Publication number
- JPS57123580A JPS57123580A JP56008926A JP892681A JPS57123580A JP S57123580 A JPS57123580 A JP S57123580A JP 56008926 A JP56008926 A JP 56008926A JP 892681 A JP892681 A JP 892681A JP S57123580 A JPS57123580 A JP S57123580A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- data
- storage device
- address
- cpu2
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE:To test the entire area of a directory memory even with the small capacity of a main storage device, by changing bit positions of addresses stored in the directory memory. CONSTITUTION:In a buffer storage device 1, a request address (a) from a CPU2 is supplied to a comparator 14 and compared with an address (b) read out of a directory memory 12 through a resetting circuit 16. When the both are coincident, a coincidence signal (c) is supplied to a control part 11, which while reading data out of a memory 13, controls a multiplexer 17 to pass the data to the CPU2. When not, the control part 11 outputs a data request signal (d) to send an address (a) to a bus 100, and data (e) is read out of a main storage device 3 and sent to the CPU2. At the same time, current readout address information is written in the memory 12, and the data (e) is also written in the memory 13. Then, an interchanging circuit 15 and the resetting circuit 16 are controlled to changes the bit positions of the memory 12 and to perform resetting on an output side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56008926A JPS6049945B2 (en) | 1981-01-26 | 1981-01-26 | buffer storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56008926A JPS6049945B2 (en) | 1981-01-26 | 1981-01-26 | buffer storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57123580A true JPS57123580A (en) | 1982-08-02 |
JPS6049945B2 JPS6049945B2 (en) | 1985-11-06 |
Family
ID=11706258
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56008926A Expired JPS6049945B2 (en) | 1981-01-26 | 1981-01-26 | buffer storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6049945B2 (en) |
-
1981
- 1981-01-26 JP JP56008926A patent/JPS6049945B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS6049945B2 (en) | 1985-11-06 |
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