JPS5680868A - Buffer memory device - Google Patents

Buffer memory device

Info

Publication number
JPS5680868A
JPS5680868A JP15766679A JP15766679A JPS5680868A JP S5680868 A JPS5680868 A JP S5680868A JP 15766679 A JP15766679 A JP 15766679A JP 15766679 A JP15766679 A JP 15766679A JP S5680868 A JPS5680868 A JP S5680868A
Authority
JP
Japan
Prior art keywords
data
memory device
address
main memory
storing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15766679A
Other languages
Japanese (ja)
Inventor
Nobuteru Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15766679A priority Critical patent/JPS5680868A/en
Publication of JPS5680868A publication Critical patent/JPS5680868A/en
Pending legal-status Critical Current

Links

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  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To make unnecessary the control of dissidence between the copy of the data of te main memory device stored and the main memory device storing data by determining whether the data is written or not in accordance with tag constituting the reading information from the main memory device.
CONSTITUTION: The request address from the central processing unit CPU1, is stored in the address register 11 of the buffer memory device CHE, it is compared with the address of the address storing memory 12, and when they are coincided with each other, through a comparator 13, a buffer memory control 14, a data storing memory 15, a multiplexer 16, a data register, etc., the data is fed to the device CPU1. When the coincidence signal is not obtained by the comparator 13, the control part 14 sends out the address and makes access to the main memory device. Thereby, when the writing judging tag 1 constructing the information read is set, the control part 14 does not carry out the writing of the read address and the data 2 to a storing memory 15. Accordingly, the control of dissidence between the copy of the data of the main memory device and the main memory device storing data becomes unnecessary.
COPYRIGHT: (C)1981,JPO&Japio
JP15766679A 1979-12-05 1979-12-05 Buffer memory device Pending JPS5680868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15766679A JPS5680868A (en) 1979-12-05 1979-12-05 Buffer memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15766679A JPS5680868A (en) 1979-12-05 1979-12-05 Buffer memory device

Publications (1)

Publication Number Publication Date
JPS5680868A true JPS5680868A (en) 1981-07-02

Family

ID=15654720

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15766679A Pending JPS5680868A (en) 1979-12-05 1979-12-05 Buffer memory device

Country Status (1)

Country Link
JP (1) JPS5680868A (en)

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